Methodology for determining the placement of decoupling capacitors in a power distribution system
    31.
    发明授权
    Methodology for determining the placement of decoupling capacitors in a power distribution system 有权
    确定配电系统中去耦电容器放置的方法

    公开(公告)号:US06789241B2

    公开(公告)日:2004-09-07

    申请号:US10284677

    申请日:2002-10-31

    IPC分类号: G06F945

    CPC分类号: G06F17/5036

    摘要: A methodology for determining the placement of decoupling capacitors in a power distribution system and system therefor is disclosed. In one embodiment, a method for determining the placement of decoupling capacitors in a power distribution system includes determining target impedance, creating a power distribution system model, performing an LC (inductive-capacitive) resonance analysis, and performing a cavity resonance analysis. During the performance of the LC resonance analysis, capacitors may be selected in order to suppress impedance peaks resulting from LC resonances. Following the LC resonance analysis, the method may place the capacitors in the power distribution system at evenly spaced intervals. During the performance of the cavity resonance analysis, the capacitors may be repositioned in the power distribution system so as to suppress cavity resonances.

    摘要翻译: 公开了一种用于确定配电系统中的去耦电容器的布置的方法及其系统。 在一个实施例中,用于确定配电系统中去耦电容器的放置的方法包括确定目标阻抗,创建配电系统模型,执行LC(电感 - 电容)谐振分析,以及执行空腔谐振分析。 在进行LC共振分析期间,可以选择电容器来抑制由LC谐振引起的阻抗峰值。 在LC共振分析之后,该方法可以以均匀间隔的间隔将电容器放置在配电系统中。 在空腔谐振分析的执行期间,可以在配电系统中重新定位电容器,以便抑制空腔谐振。

    276-PIN BUFFERED MEMORY CARD WITH ENHANCED MEMORY SYSTEM INTERCONNECT
    32.
    发明申请
    276-PIN BUFFERED MEMORY CARD WITH ENHANCED MEMORY SYSTEM INTERCONNECT 有权
    276密钥缓存的存储卡,具有增强的存储器系统互连

    公开(公告)号:US20130301207A1

    公开(公告)日:2013-11-14

    申请号:US13466682

    申请日:2012-05-08

    IPC分类号: G06F1/16 H05K1/11

    摘要: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card.

    摘要翻译: 一个实施例是一种存储卡,其包括具有第一侧和第二侧的矩形印刷电路卡,第一长度在151.35和161.5毫米之间,第一和第二端的第二长度小于第一长度。 存储卡还包​​括沿着矩形印刷电路卡的沿着矩形印刷电路卡的长度延伸的第一边沿第一侧延伸的第一多个销,第二侧上延伸的第二多个销在第一侧上延伸 矩形印刷电路卡的边缘,以及定位键,其中心位于矩形印刷电路卡的第一边缘上,并且距离矩形印刷电路卡的第一端位于94.0和95.5毫米之间。

    System and Method of Integrated Circuit Control for in Situ Impedance Measurement
    33.
    发明申请
    System and Method of Integrated Circuit Control for in Situ Impedance Measurement 审中-公开
    用于现场阻抗测量的集成电路控制系统和方法

    公开(公告)号:US20080224714A1

    公开(公告)日:2008-09-18

    申请号:US11685226

    申请日:2007-03-13

    IPC分类号: G01R27/02

    摘要: A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.

    摘要翻译: 一种用于原位阻抗测量的集成电路控制的系统和方法,包括在时钟逻辑型集成电路中具有多个功能分区的系统,功能分区具有通信控制器和调制门,调制门接收时钟信号, 调制信号并产生用于功能分区的调制时钟信号; 所述通信控制器中的至少一个接收带内信号并选择性地将所述带内信号传送到所述其他通信控制器; 并且功能分区中的至少一个具有调制器,调制器接收时钟信号和调制控制信号并产生调制信号。

    Measuring microprocessor susceptibility to internal noise generation
    34.
    发明授权
    Measuring microprocessor susceptibility to internal noise generation 失效
    测量微处理器对内部噪声产生的敏感性

    公开(公告)号:US07313747B2

    公开(公告)日:2007-12-25

    申请号:US11388002

    申请日:2006-03-23

    IPC分类号: G01R31/30

    CPC分类号: G01R31/318378

    摘要: A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.

    摘要翻译: 提供了计算机实现的方法,测试系统,计算机可用程序代码和装置,用于测量微处理器对内部噪声的敏感性。噪声发生器调制时钟信号以在微处理器内的目标组件上产生噪声。 函数发生器在微处理器内的多个功能部件上执行微处理器功能。 然后测量多个功能组件上的最大执行频率,并且确定功能组件易于产生噪声的一组频率范围。

    276-pin buffered memory card with enhanced memory system interconnect
    35.
    发明授权
    276-pin buffered memory card with enhanced memory system interconnect 有权
    276针缓冲存储卡,具有增强的内存系统互连

    公开(公告)号:US09357649B2

    公开(公告)日:2016-05-31

    申请号:US13466682

    申请日:2012-05-08

    摘要: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card.

    摘要翻译: 一个实施例是一种存储卡,其包括具有第一侧和第二侧的矩形印刷电路卡,第一长度在151.35和161.5毫米之间,第一和第二端的第二长度小于第一长度。 存储卡还包​​括沿着矩形印刷电路卡的沿着矩形印刷电路卡的长度延伸的第一边沿第一侧延伸的第一多个销,第二侧上延伸的第二多个销在第一侧上延伸 矩形印刷电路卡的边缘,以及定位键,其中心位于矩形印刷电路卡的第一边缘上,并且距离矩形印刷电路卡的第一端位于94.0和95.5毫米之间。

    REDUNDANT CLOCK CHANNEL FOR HIGH RELIABILITY CONNECTORS
    36.
    发明申请
    REDUNDANT CLOCK CHANNEL FOR HIGH RELIABILITY CONNECTORS 失效
    用于高可靠性连接器的冗余时钟通道

    公开(公告)号:US20120120577A1

    公开(公告)日:2012-05-17

    申请号:US12946328

    申请日:2010-11-15

    IPC分类号: G06F1/16

    CPC分类号: G06F1/185 G06F1/10

    摘要: A memory module configured to connect to a slot of a data processing system. A set of tabs is connected to the module and configured to electrically connect the module to the slot and to electrically connect the module to a clock of the data processing system. The set of tabs includes a first tab, a second tab, a third tab, and a fourth tab. The first tab and the second tab are opposite the third tab and the fourth tab. The first tab comprises a positive type tab, the second tab comprises a negative type tab, the third tab comprises a positive type tab, and the fourth tab comprises a negative type tab. The first and third tabs are configured to provide a first electrical connection to the clock. The second and fourth tabs are configured to provide a second electrical connection to the clock. Together, the first, second, third, and fourth tabs comprise two dual tabs.

    摘要翻译: 配置为连接到数据处理系统的时隙的存储器模块。 一组标签连接到模块并且被配置为将模块电连接到插槽并且将模块电连接到数据处理系统的时钟。 该组标签包括第一标签,第二标签,第三标签和第四标签。 第一个选项卡和第二个选项卡与第三个选项卡和第四个选项卡相对。 第一标签包括一个正型标签,该第二标签包括一个负型标签,该第三标签包括一个正型标签,该第四标签包括一个负型标签。 第一和第三选项卡被配置为提供到时钟的第一电连接。 第二和第四选项卡被配置为提供与时钟的第二电连接。 一起,第一,第二,第三和第四标签包括两个双标签。