利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.021 秒)

    Measuring microprocessor susceptibility to internal noise generation
    1.
    发明授权
    Measuring microprocessor susceptibility to internal noise generation 失效
    测量微处理器对内部噪声产生的敏感性

    公开(公告)号：US07313747B2

    公开(公告)日：2007-12-25

    申请号：US11388002

    申请日：2006-03-23

    申请人： Sungjun Chun ,  Timothy M. Skergan ,  Ching Lung Tong ,  Roger Donell Weekly

    发明人： Sungjun Chun ,  Timothy M. Skergan ,  Ching Lung Tong ,  Roger Donell Weekly

    IPC分类号： G01R31/30

    CPC分类号： G01R31/318378

    摘要： A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.

    摘要翻译： 提供了计算机实现的方法，测试系统，计算机可用程序代码和装置，用于测量微处理器对内部噪声的敏感性。噪声发生器调制时钟信号以在微处理器内的目标组件上产生噪声。 函数发生器在微处理器内的多个功能部件上执行微处理器功能。 然后测量多个功能组件上的最大执行频率，并且确定功能组件易于产生噪声的一组频率范围。

    System and Method of Integrated Circuit Control for in Situ Impedance Measurement
    2.
    发明申请
    System and Method of Integrated Circuit Control for in Situ Impedance Measurement 审中-公开
    用于现场阻抗测量的集成电路控制系统和方法

    公开(公告)号：US20080224714A1

    公开(公告)日：2008-09-18

    申请号：US11685226

    申请日：2007-03-13

    申请人： Tanit Virutchapunt ,  Sungjun Chun ,  Timothy M. Skergan ,  Roger D. Weekly

    发明人： Tanit Virutchapunt ,  Sungjun Chun ,  Timothy M. Skergan ,  Roger D. Weekly

    IPC分类号： G01R27/02

    CPC分类号： G01R31/31922 ,  G01R27/02 ,  G01R31/31937

    摘要： A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.

    摘要翻译： 一种用于原位阻抗测量的集成电路控制的系统和方法，包括在时钟逻辑型集成电路中具有多个功能分区的系统，功能分区具有通信控制器和调制门，调制门接收时钟信号， 调制信号并产生用于功能分区的调制时钟信号; 所述通信控制器中的至少一个接收带内信号并选择性地将所述带内信号传送到所述其他通信控制器; 并且功能分区中的至少一个具有调制器，调制器接收时钟信号和调制控制信号并产生调制信号。

    Reducing crosstalk in the design of module nets
    4.
    发明授权
    Reducing crosstalk in the design of module nets 有权
    减少模块网设计中的串扰

    公开(公告)号：US08407644B2

    公开(公告)日：2013-03-26

    申请号：US12537767

    申请日：2009-08-07

    申请人： Dulce M. Altabella Cabrera ,  Sungjun Chun ,  Anand Haridass ,  Tingdong Zhou

    发明人： Dulce M. Altabella Cabrera ,  Sungjun Chun ,  Anand Haridass ,  Tingdong Zhou

    IPC分类号： G06F17/50

    CPC分类号： H01L23/5386 ,  G06F17/5077 ,  G06F2217/82 ,  H01L23/5222 ,  H01L23/552 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192

    摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.

    摘要翻译： 一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。 在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。 特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。 此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT
    5.
    发明申请
    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
    具有条带划分的参考平面电路的电路制造和设计技术

    公开(公告)号：US20120331429A1

    公开(公告)日：2012-12-27

    申请号：US13603732

    申请日：2012-09-05

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

    CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE BY VARIABLE-WIDTH MESH PLANE STRUCTURES
    6.
    发明申请
    CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE BY VARIABLE-WIDTH MESH PLANE STRUCTURES 有权
    可变宽度MESH PLANE结构在多层包装中的信号层之间的降噪减少

    公开(公告)号：US20120125677A1

    公开(公告)日：2012-05-24

    申请号：US12952152

    申请日：2010-11-22

    申请人： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

    发明人： Jinwoo Choi ,  Sungjun Chun ,  Jason L. Frankel ,  Paul R. Walling ,  Roger D. Weekly

    IPC分类号： H05K1/11 ,  H05K3/10

    CPC分类号： H05K1/0224 ,  G06F17/5081 ,  H05K1/116 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/53022

    摘要： A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.

    摘要翻译： 网格层的网格线段的第一选择是第一宽度，并且网格层的网格线段的第二选择具有第二宽度，其中第二宽度大于第一宽度。 第二宽度的网格线段的第二选择与信号层中可能引入串扰的信号线的选择平行地布置，其中遮蔽信号线选择的网线段的加宽增加了 与信号相关联的返回电流将在更宽的网格线段中流动，从而增加了包含与信号相关联的电磁场的可能性，使得与其他信号的串扰减少或包含。

    Detecting open ground connections in surface mount connectors
    7.
    发明授权
    Detecting open ground connections in surface mount connectors 失效
    检测表面贴装连接器中的开放接地连接

    公开(公告)号：US07868608B2

    公开(公告)日：2011-01-11

    申请号：US12420089

    申请日：2009-04-08

    申请人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    发明人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    IPC分类号： G01R31/28

    CPC分类号： G01R31/026 ,  G01R31/043 ,  G01R31/2812 ,  H05K3/341

    摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.

    摘要翻译： 设备可以包括用于连接到印刷电路板的电流源。 该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。 另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。 热监测模块可用于识别不正确的物理连接。

    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT
    8.
    发明申请
    CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT 失效
    具有条带划分的参考平面电路的电路制造和设计技术

    公开(公告)号：US20100261346A1

    公开(公告)日：2010-10-14

    申请号：US12823316

    申请日：2010-06-25

    申请人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H01L21/768 ,  G06F17/50

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持 信号路径导体。

    Detecting Open Ground Connections in Surface Mount Connectors
    9.
    发明申请
    Detecting Open Ground Connections in Surface Mount Connectors 失效
    检测表面贴装连接器中的开放接地连接

    公开(公告)号：US20100259289A1

    公开(公告)日：2010-10-14

    申请号：US12420089

    申请日：2009-04-08

    申请人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    发明人： Anand Haridass ,  Jesus Montanez ,  Xiaomin Shen ,  Sungjun Chun

    IPC分类号： G01R31/02 ,  H01L25/00

    CPC分类号： G01R31/026 ,  G01R31/043 ,  G01R31/2812 ,  H05K3/341

    摘要： A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection.

    摘要翻译： 设备可以包括用于连接到印刷电路板的电流源。 该装置还可以包括用于连接到印刷电路板的表面安装连接器的第一FET开关组件和第二FET开关组件。 另外，该装置可以包括连接到第一FET开关组和第二FET开关组的FET控制器。 FET控制器可以用于将第一FET和第二FET连接到表面安装连接器的第一区域。 FET控制器可以被配置为将电流提供给表面安装连接器的第一区域，以产生不正确连接的接地引脚的至少一个连续的热标记特性。 热监测模块可用于识别不正确的物理连接。