公开(公告)号：US11164611B1

公开(公告)日：2021-11-02

申请号：US16906647

申请日：2020-06-19

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia

IPC: G11C7/00 ,  G11C7/08 ,  H03K19/0185 ,  G11C7/22 ,  G11C7/10 ,  H03K3/037

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.

公开(公告)号：US11018653B1

公开(公告)日：2021-05-25

申请号：US16866307

申请日：2020-05-04

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Qi Ye

IPC: H03K3/012 ,  H03K3/037

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

公开(公告)号：US10742201B2

公开(公告)日：2020-08-11

申请号：US16243954

申请日：2019-01-09

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: G11C7/22 ,  H03K3/037 ,  G06F1/28 ,  G06F1/08

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US20200106425A1

公开(公告)日：2020-04-02

申请号：US16243954

申请日：2019-01-09

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: H03K3/037 ,  G06F1/08 ,  G06F1/28

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US10461747B2

公开(公告)日：2019-10-29

申请号：US15710406

申请日：2017-09-20

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Michael R Seningen ,  Ajay Bhatia

IPC: H03K19/00 ,  H03K5/134

Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.

公开(公告)号：US10261563B1

公开(公告)日：2019-04-16

申请号：US15839317

申请日：2017-12-12

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

IPC: H03K17/16 ,  G06F1/3206 ,  G06F17/50 ,  H03K17/62 ,  H03K17/22

Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.