公开(公告)号：US20160247249A1

公开(公告)日：2016-08-25

申请号：US15049392

申请日：2016-02-22

Applicant: ARM Limited

Inventor： Peter William Harris ,  Sandeep Kakarlapudi ,  Andreas Due Engh-Halstvedt

IPC: G06T1/20 ,  G06T9/00 ,  G06T11/00

CPC classification number: G06T9/00 ,  G06T11/40 ,  G06T15/005

Abstract: A graphics processing pipeline includes processing circuitry. The processing circuitry is configured to determine attribute information for an object to be rendered for a set of sampling points from a compressed representation of attribute information associated with the object, when the set of sampling points is being processed by the graphics processing pipeline to generate a render output. The processing circuitry is also configured to use the determined attribute information to control the processing of the set of sampling points by the graphics processing pipeline when generating the render output.

Abstract translation: 图形处理流水线包括处理电路。 所述处理电路被配置为当所述采样点集合被所述图形处理流水线处理以产生一个或多个采样点时，从与所述对象相关联的属性信息的压缩表示中，为一组采样点确定要渲染的对象的属性信息 渲染输出。 处理电路还被配置为使用所确定的属性信息来在生成渲染输出时由图形处理流水线控制该组采样点的处理。

公开(公告)号：US09218793B2

公开(公告)日：2015-12-22

申请号：US13658997

申请日：2012-10-24

Applicant: ARM LIMITED

Inventor： Sandeep Kakarlapudi ,  Jorn Nystad

IPC: G09G5/39 ,  G09G5/377 ,  G09G5/36 ,  G06T15/00 ,  G06T11/40

CPC classification number: G09G5/377 ,  G06T11/40 ,  G06T15/005 ,  G09G5/363 ,  G09G2360/06 ,  G09G2360/122

Abstract: A tile-based graphics processor includes tile processing circuitry that has both a tile buffer and a per-pixel general purpose data store. The per-pixel general purpose data store is read accessible and write accessible by the tile processing circuitry to store intermediate values. These intermediate values are generated by the tile processing circuitry and then consumed by the tile processing circuitry to generate the output values for the tile being processed.

Abstract translation: 基于瓦片的图形处理器包括具有瓦片缓冲器和每像素通用数据存储器的瓦片处理电路。 每像素通用数据存储器被读取可访问并且可由片处理电路写入以存储中间值。 这些中间值由瓦片处理电路产生，然后由瓦片处理电路消耗以产生正被处理的瓦片的输出值。

公开(公告)号：US20140327671A1

公开(公告)日：2014-11-06

申请号：US13875822

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Sandeep Kakarlapudi ,  Michael Stokes

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005

Abstract: A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.

Abstract translation: 包括光栅化器3，渲染器6，瓦片缓冲器10，写入级13和可编程处理级14的基于瓦片的图形处理流水线1.瓦片缓冲器10存储用于延迟着色操作和可编程 处理阶段14可操作以在图形程序指令的控制下从存储在瓦片缓冲器10中的延迟着色操作的一组多个渲染目标中的两个或更多个读取数据，使用读取的数据执行延迟着色处理操作 并将处理操作的结果写入瓦片缓冲器10中的输出渲染目标，或写入外部存储器。