Dual layer bus architecture for system-on-a-chip
    31.
    发明授权
    Dual layer bus architecture for system-on-a-chip 有权
    用于片上系统的双层总线架构

    公开(公告)号:US07508981B2

    公开(公告)日:2009-03-24

    申请号:US11200039

    申请日:2005-08-10

    申请人: Hyun-Sang Park

    发明人: Hyun-Sang Park

    IPC分类号: G06K9/00 G06F13/00 G06F13/14

    CPC分类号: G06F13/40

    摘要: A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary memory operating independently of the main bus and adapted to connect the dual master module to a high-speed secondary memory.

    摘要翻译: 公开了一种用于片上系统(SOC)的双层总线架构。 总线架构包括适于将微处理器,图像捕获模块和双主模块连接到高密度存储器的主总线和独立于主总线操作的辅助存储器,并且适于将双主模块连接到高速存储器, 速度二次记忆。

    Video encoding method and video encoder for improving performance
    32.
    发明申请
    Video encoding method and video encoder for improving performance 有权
    视频编码方法和视频编码器,以提高性能

    公开(公告)号:US20060209962A1

    公开(公告)日:2006-09-21

    申请号:US11436016

    申请日:2006-05-17

    摘要: Video encoding methods and video encoders that provide improved performance while reducing power consumption. In one aspect, a video encoding method comprises the steps of outputting a parameter for a slice of a current frame, wherein the slice comprises a plurality of macroblocks, and the parameter comprises an address of a first macroblock of the slice, an address of a search area on a previous frame, a search area corresponding to a current macroblock, and a number of macroblocks comprising the slice; processing the slice by consecutively encoding and decoding each macroblock of the slice in response to the parameter; and outputting an interrupt signal for the current frame, when encoding and decoding for each macroblock of the all slices is consecutively performed so that encoding for the current frame is completed.

    摘要翻译: 视频编码方法和视频编码器在降低功耗的同时提供更好的性能。 一方面,一种视频编码方法包括以下步骤:输出当前帧的片段的参数,其中片包括多个宏块,并且该参数包括片的第一宏块的地址, 前一帧的搜索区域,与当前宏块对应的搜索区域以及包括该切片的宏块数量; 通过响应于该参数连续编码和解码片的每个宏块来处理片; 并输出当前帧的中断信号,当对全部片段的每个宏块进行编码和解码时,连续执行,使得当前帧的编码完成。

    Source driver and source line driving method for driving a flat panel display
    33.
    发明申请
    Source driver and source line driving method for driving a flat panel display 审中-公开
    用于驱动平板显示器的源驱动器和源极线驱动方法

    公开(公告)号:US20050169075A1

    公开(公告)日:2005-08-04

    申请号:US11030831

    申请日:2005-01-08

    申请人: Hyun-Sang Park

    发明人: Hyun-Sang Park

    IPC分类号: G09G3/36 G11C7/00

    摘要: A source driver and a source line driving method for driving a flat panel display are provided. The source driver controls bias voltages of buffers that provide buffering for R, G, and B color signals using input/output signals generated by the flat panel display, or controls precharge voltages or precharge voltage widths of the respective buffers for buffering the R, G, and B color signals using inner precharge control circuits. The driving abilities of the output pins of the source driver transmitting the R, G, and B color signals are independently controlled, and therefore, identical charge characteristics can be obtained by respective R, G, and B pixels having different loads.

    摘要翻译: 提供了用于驱动平板显示器的源极驱动器和源极线驱动方法。 源极驱动器控制使用由平板显示器产生的输入/输出信号为R,G和B彩色信号提供缓冲的缓冲器的偏置电压,或者控制用于缓冲R,G的各个缓冲器的预充电电压或预充电电压宽度 ,以及使用内部预充电控制电路的B色信号。 传输R,G和B颜色信号的源极驱动器的输出引脚的驱动能力被独立地控制,因此可以通过具有不同负载的相应的R,G和B像素获得相同的电荷特性。