公开(公告)号：US20110157129A1

公开(公告)日：2011-06-30

申请号：US12974584

申请日：2010-12-21

申请人： Hyun-Min SONG ,  Young-Suk Son ,  Ji-Hum Kim ,  Joon-Ho Na

发明人： Hyun-Min SONG ,  Young-Suk Son ,  Ji-Hum Kim ,  Joon-Ho Na

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/36 ,  G09G3/3685 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2320/0252

摘要： A source driver circuit of a liquid crystal display device including a gamma buffer. The gamma buffer includes a differential amplification section configured to differentially amplify an input signal; a current mirror section configured to operate as a current mirror; an enable section configured to convert the differential amplification section from a standby mode to an enable mode by a bias voltage; a power drop speed improvement section configured to respectively connect drains of the two PMOS transistors of the current mirror section and drains of the two NMOS transistors of the differential amplification section through two diode coupling type MOS transistors, and shorten a recovery time after a power drop; and an output section configured to be determined in a bias level thereof by the bias voltage and generate an output voltage according to a voltage of a downstream node on one side of the current mirror section.

摘要翻译： 一种包括伽马缓冲器的液晶显示装置的源极驱动电路。 伽马缓冲器包括被配置为差分放大输入信号的差分放大部分; 配置为作为电流镜操作的电流镜部; 使能部分，被配置为通过偏置电压将差分放大部分从待机模式转换为使能模式; 功率下降速度改善部分，被配置为通过两个二极管耦合型MOS晶体管分别连接电流镜部分的两个PMOS晶体管的漏极和差分放大部分的两个NMOS晶体管的漏极，并且在掉电之后缩短恢复时间 ; 以及输出部，被配置为通过偏置电压在其偏置电平中确定，并且根据当前镜部的一侧上的下游节点的电压产生输出电压。

公开(公告)号：US06285230B1

公开(公告)日：2001-09-04

申请号：US09544215

申请日：2000-04-07

申请人： Joon-Ho Na

发明人： Joon-Ho Na

IPC分类号： H03H1126

CPC分类号： H03K5/133

摘要： An input buffer circuit compensates for a data hold time and reduces an operational current by implementing a delay operation with transistors having a long channel when the input buffer circuit is driven by a high external voltage. The input buffer circuit includes a delay unit to delay an input signal, the delay unit being powered by an external power voltage and having an associated variable delay which is varied according to a detection signal and the external power voltage, the detection signal indicating whether the external power voltage is high or low.

摘要翻译： 输入缓冲器电路补偿数据保持时间，并且当输入缓冲器电路被高外部电压驱动时，通过对具有长通道的晶体管实施延迟操作来减小工作电流。 所述输入缓冲电路包括延迟单元，用于延迟输入信号，所述延迟单元由外部电源电压供电并具有根据检测信号和所述外部电源电压而变化的相关联的可变延迟，所述检测信号指示是否 外部电源电压高或低。