公开(公告)号：US08078843B2

公开(公告)日：2011-12-13

申请号：US12023155

申请日：2008-01-31

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/30

CPC分类号： G06F9/30079 ,  G06F9/30145 ,  G06F9/3867

摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. The enhanced DRAIN instruction enables its use to be more granular and to have minimal impact with respect to each individual use.

摘要翻译： 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。 增强的DRAIN指令使其使用更细致，对每个用户的影响最小。

公开(公告)号：US20090240921A1

公开(公告)日：2009-09-24

申请号：US12051486

申请日：2008-03-19

申请人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

发明人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

IPC分类号： G06F9/30

CPC分类号： G06F9/3865 ,  G06F9/3836 ,  G06F9/3842

摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

摘要翻译： 提供了一种计算机处理系统。 计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。 处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。 管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

公开(公告)号：US20090217005A1

公开(公告)日：2009-08-27

申请号：US12037861

申请日：2008-02-26

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F9/3836

摘要： A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.

摘要翻译： 一种用于选择性地加速早期指令处理的方法，包括接收在处理器流水线的执行阶段中正常处理的指令数据，其中指令数据的配置允许指令数据的处理从执行阶段加速到地址 在处理器流水线中比执行阶段更早发生的生成阶段，确定指令数据是否可以被分派到要处理的地址生成阶段，而不会由于处理指令数据所需的处理资源的不可用而被延迟 地址生成阶段，如果能够由于处理资源的不可用而被分派而不被延迟，则在地址生成阶段调度要处理的指令数据，并且如果不能在执行阶段调度要处理的指令数据 由于你而不被推迟 处理资源的可用性，其中使用地址生成互锁方案选择性地加速指令数据的处理。 相应的系统和计算机程序产品。

公开(公告)号：US20090198980A1

公开(公告)日：2009-08-06

申请号：US12023155

申请日：2008-01-31

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/30

CPC分类号： G06F9/30079 ,  G06F9/30145 ,  G06F9/3867

摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.

摘要翻译： 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。

公开(公告)号：US08516228B2

公开(公告)日：2013-08-20

申请号：US12051486

申请日：2008-03-19

申请人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

发明人： Khary J. Alexander ,  Michael Billeci ,  Fadi Y. Busaba ,  Bruce C. Giamei

IPC分类号： G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3836 ,  G06F9/3842

摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

摘要翻译： 提供了一种计算机处理系统。 计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。 处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。 管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

公开(公告)号：US20110167244A1

公开(公告)日：2011-07-07

申请号：US13050484

申请日：2011-03-17

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

公开(公告)号：US08407453B2

公开(公告)日：2013-03-26

申请号：US13273320

申请日：2011-10-14

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/30

CPC分类号： G06F9/30079 ,  G06F9/30145 ,  G06F9/3867

摘要： Processing within a computing environment is facilitated using an extended DRAIN instruction. An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.

摘要翻译： 使用扩展DRAIN指令便于计算环境内的处理。 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。

公开(公告)号：US20120036338A1

公开(公告)日：2012-02-09

申请号：US13273320

申请日：2011-10-14

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C. Giamei ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/30

CPC分类号： G06F9/30079 ,  G06F9/30145 ,  G06F9/3867

摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired.

摘要翻译： 扩展DRAIN指令用于在计算环境中停止处理。 该指令包括处理被停止的一个或多个处理阶段的指示。 它还包括一个控制，允许根据需要使处理停滞在额外的周期。

公开(公告)号：US20090210675A1

公开(公告)日：2009-08-20

申请号：US12034042

申请日：2008-02-20

申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

公开(公告)号：US20130339666A1

公开(公告)日：2013-12-19

申请号：US13524471

申请日：2012-06-15

申请人： Gregory W. Alexander ,  Brian D. Barrick ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Edward T. Malley ,  Chung-Lung K. Shum

发明人： Gregory W. Alexander ,  Brian D. Barrick ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Edward T. Malley ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/384

摘要： A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag.