公开(公告)号：US06446190B1

公开(公告)日：2002-09-03

申请号：US09267570

申请日：1999-03-12

申请人： Edwin F. Barry ,  Gerald G. Pechanek ,  Patrick R. Marchand

发明人： Edwin F. Barry ,  Gerald G. Pechanek ,  Patrick R. Marchand

IPC分类号： G06F935

CPC分类号： G06F9/3885 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/30141 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/342 ,  G06F9/345 ,  G06F9/35 ,  G06F9/3552 ,  G06F9/3842 ,  G06F9/3853

摘要： A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibilty in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions. The use of RFI in a processor containing multiple heterogeneous execution units which operate in parallel, such as VLIW or iVLIW processors, allows for efficient pipelining of algorithms across multiple execution units while minimizing the number of VLIW instructions required.

摘要翻译： 使用访问寄存器文件中的数据块的双重间接方法来允许有效的实现而不使用专门的向量处理硬件。 此外，寄存器寻址的自动修改不会与单个向量指令相关，也不会重复或循环指令。 相反，称为寄存器文件索引（RFI）的技术允许完全编程器灵活地控制块数据操作设施，并提供将非RFI指令与RFI指令混合的能力。 块数据操作设施嵌入在iVLIW ManArray架构中，允许其在整个指令集架构中被广泛使用，而不需要专门的向量指令，或仅在重复或循环指令时受限制。 在包含多个并行运行的异构执行单元（例如VLIW或iVLIW处理器）的处理器中使用RFI允许在多个执行单元之间有效地流水线算法，同时最小化所需的VLIW指令数量。

公开(公告)号：US06356994B1

公开(公告)日：2002-03-12

申请号：US09350191

申请日：1999-07-09

申请人： Edwin F. Barry ,  Gerald G. Pechanek

发明人： Edwin F. Barry ,  Gerald G. Pechanek

IPC分类号： G06F1500

CPC分类号： G06F9/382 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/32 ,  G06F9/3552 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3842 ,  G06F9/3853

摘要： An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses. These addressing techniques provide tremendous flexibility for VLIW instruction execution.

公开(公告)号：US06321322B1

公开(公告)日：2001-11-20

申请号：US09543473

申请日：2000-04-05

申请人： Gerald G. Pechanek ,  Edwin F. Barry ,  Juan Guillermo Revilla ,  Larry D. Larsen

发明人： Gerald G. Pechanek ,  Edwin F. Barry ,  Juan Guillermo Revilla ,  Larry D. Larsen

IPC分类号： G06F1580

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30178 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3885

摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

摘要翻译： 分层指令集架构（ISA）提供可插拔指令集功能和阵列处理器的支持。 术语pluggable来自程序员的观点，并且涉及可以容易地添加到处理器架构中以用于代码密度和性能增强的指令组。 本文所述的一个具体方面是独特的压缩指令集，其允许程序员能够通过任务为任务动态地创建一组压缩指令，以提高控制和并行代码密度的主要目的。 这些压缩指令是可并行的，因为它们不特别地限于控制代码应用，而是可以在阵列处理器中的处理元件（PE）中执行。 ManArray系列处理器专为此动态压缩指令集功能而设计，并且还支持从一个到N个PE的可扩展阵列。 此外，ManArray ISA被定义为ISA的层次结构，其允许未来指令能力的增长并且支持在指令层次结构内的多个指令的打包。

公开(公告)号：US06173389B2

公开(公告)日：2001-01-09

申请号：US09205588

申请日：1998-12-04

申请人： Gerald G. Pechanek ,  Juan Guillermo Revilla ,  Edwin F. Barry

发明人： Gerald G. Pechanek ,  Juan Guillermo Revilla ,  Edwin F. Barry

IPC分类号： G06F1580

CPC分类号： G06F9/3842 ,  G06F9/3017 ,  G06F9/3822 ,  G06F9/3853

摘要： A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit's VIM can be independently addressed thereby removing duplicate SIWs within the functional unit's VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.

摘要翻译： 流水线数据处理单元包括指令定序器和能够并行执行n个操作的n个功能单元。 指令定序器包括用于存储在涉及并行执行两个或多个功能单元的操作中使用的非常长指令字（VLIW）的随机存取存储器。 每个VLIW包括多个短指令字（SIW），其中每个SIW对应于与唯一功能单元相关联的唯一类型的指令。 VLIW通过在每个地址或条目中加载和连接SIW来组成VLIW存储器。 VLIW通过执行VLIW（XV）指令执行。 通过使用包含在XV1指令中的掩码字段，可以在VLIW存储器地址处压缩iVLIW，该掩码字段指定在执行VLIW期间启用或禁用哪些功能单元。 每次执行XV1指令时，可以更改掩码，每次执行时都可以有效地修改VLIW。 VLIW存储器（VIM）可以被进一步划分成各自与功能解码和执行单元相关联的存储器。 通过第二执行VLIW指令XV2，可以独立地对每个功能单元的VIM进行寻址，从而去除功能单元的VIM内的重复SIW。 这提供了VLIW存储器的进一步优化，从而允许在成本敏感的应用中使用较小的VLIW存储器。