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公开(公告)号:US20200382223A1
公开(公告)日:2020-12-03
申请号:US16881657
申请日:2020-05-22
Inventor: Hyuk KIM , Hyung-IL PARK , Tae Wook KANG , Sung Eun KIM , Mi Jeong PARK , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In Gi LIM
IPC: H04B13/00 , G06F16/9535 , G06F3/044 , H04B5/00
Abstract: A user device connected to an edge device, based on a touch of a user includes an electrode in touch with a body of the user, a human body communication module that receives a first signal from the edge device through the body and the electrode, an operation processing module that acquires identification information, location information, version information of the edge device, and time information at which the first signal is received, from the first signal, and a memory module that stores the identification information, the location information, the version information, and the time information, as part of life log information.
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32.
公开(公告)号:US20190392291A1
公开(公告)日:2019-12-26
申请号:US16445925
申请日:2019-06-19
Inventor: Seong Mo PARK , Jae-Jin LEE , Sung Eun KIM , Kyung Hwan PARK , Mi Jeong PARK , Young Hwan BAE , Kwang IL OH , Byounggun CHOI
IPC: G06N3/04
Abstract: Provided is an electronic circuit for implementing a generative adversarial neural network. The electronic circuit includes a spike converter, a spike image generator, a spike image converter, and an image discriminator. The spike converter generates a first signal including spike signals. The number of the spike signals is determined based on first data associated with second data within a reference time interval. The spike image generator generates a second signal including spike signals being selected based on a weight among the spike signals of the first signal. The image converter converts the spike signals of the second signal to generate third data being represented in an analog domain. The image discriminator provides the spike image generator with result data being associated with a difference between a value of the third data and a value of the second data. The image generator determines the weight based on the result data.
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33.
公开(公告)号:US20190335984A1
公开(公告)日:2019-11-07
申请号:US16402164
申请日:2019-05-02
Inventor: Mi Jeong PARK , Hyung-IL PARK , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Kwang IL OH , Jae-Jin LEE , In Gi LIM
Abstract: Provided is and electrode selection device communicating with a capsule endoscope. The device includes an analog front end configured to recover first data based on first signals transmitted from the capsule endoscope to a first electrode and a second electrode, recover second data based on second signals transmitted from the capsule endoscope to the first electrode and a third electrode, and recover third data based on third signals transmitted from the capsule endoscope to the second electrode and the third electrode, and a digital receiver configured to calculate a first correlation value between the first and second electrodes, a second correlation value between the first and third electrodes, and a third correlation value between the second and third electrodes based on the first to third data. The digital receiver calculates, among the first to third correlation values, a first correlation sum obtained by adding first and second correlation values generated using the first electrode, a second correlation sum obtained by adding the first and third correlation values generated using the second electrode, and a third correlation sum obtained by adding the second and third correlation values generated using the third electrode, and selects a receiving electrode pair among the first to third electrodes based on the first to third correlation sums.
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公开(公告)号:US20180211165A1
公开(公告)日:2018-07-26
申请号:US15828153
申请日:2017-11-30
Inventor: Kwang IL OH , Sung Eun KIM , Seong Mo PARK , Hyung-IL PARK , Joo Hyun LEE
CPC classification number: G06N3/08 , G06N3/04 , G06N3/063 , H03K3/017 , H03K3/0315 , H03K21/026
Abstract: Provided is a neuromorphic arithmetic device. The neuromorphic arithmetic device may include a synapse circuit, a metal line having an inherent capacitance component, an oscillator, a comparator, and a capacitance calibrator. The synapse circuit may be configured to perform a multiplication operation on a PWM signal and a weight to generate a current. The metal line may include a metal line capacitor in which a charge of the current is stored. The oscillator generates a plurality of pulses on the basis of the charge stored in the metal line capacitor. The comparator may compare a frequency of the plurality of pulses and a target frequency, and may generate a control signal on the basis of a result of the comparison. The capacitance calibrator may adjust a capacitance value of the metal line capacitor on the basis of the control signal.
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35.
公开(公告)号:US20240428047A1
公开(公告)日:2024-12-26
申请号:US18422776
申请日:2024-01-25
Inventor: Kwang IL OH , Tae Wook KANG , Hyuk KIM , Jae-Jin LEE
Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates first and second input spike signals, a synapse circuit that generates a first current based on the first input spike signal and a weight and generates a second current based on the second input spike signal and the weight, a capacitor that forms a first membrane voltage based on the first current, and a neuron circuit including a comparator and that resets the first membrane voltage, and after the capacitor further forms a second membrane voltage based on the second current, and the comparator includes a first input terminal and a second input terminal, receives the first membrane voltage through the first input terminal and a reference voltage through the second input terminal, generates a first spike signal based on a first comparison operation of the first membrane voltage and the reference voltage.
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公开(公告)号:US20240378429A1
公开(公告)日:2024-11-14
申请号:US18406349
申请日:2024-01-08
Inventor: Kwang IL OH , Tae Wook KANG , Hyuk KIM , Jae-Jin LEE
IPC: G06N3/049
Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a synapse circuit that outputs a current based on the input spike signal and a weight, a capacitor that forms a membrane voltage based on the current, and a neuron circuit that generates an output spike signal based on the membrane voltage, and the neuron circuit includes a first comparator that generates an intermediate spike signal based on the membrane voltage and a first reference voltage, and a second comparator that generates the output spike signal based on the intermediate spike signal, the membrane voltage, and a second reference voltage that is different from the first reference voltage.
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公开(公告)号:US20230306247A1
公开(公告)日:2023-09-28
申请号:US18073830
申请日:2022-12-02
Inventor: In San JEON , Hyuk KIM , Jae-Jin LEE , Tae Wook KANG , Sung Eun KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH
Abstract: Disclosed is a neuron circuit, which includes a first bias circuit that adds a bias current to an input current to generate a biased input current, a logarithm-based neuron calculation circuit that performs a logarithm calculation on an amount of current of the biased input current to generate an input logarithm value and generates a biased output voltage by performing a logarithm-based Hodgkin-Huxley model calculation based on the input logarithm value, and a second bias circuit that adds a bias voltage to the biased output voltage to generate an output voltage.
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公开(公告)号:US20230140256A1
公开(公告)日:2023-05-04
申请号:US17965393
申请日:2022-10-13
Inventor: Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In San JEON
Abstract: Disclosed is an electronic device that supports a neural network including a neuron array including neurons, a row address encoder that receives spike signals from neurons and outputs request signals in response to the received spike signals, and a row arbiter tree that receives request signals from the row address encoder and outputs response signals in response to the received request signals. The row arbiter tree includes a first arbiter that arbitrates first and second request signals among request signals, a first latch circuit that stores a state of the first arbiter, a second arbiter that arbitrates third and fourth request signals among request signals, a second latch circuit that stores a state of the second arbiter, and a third arbiter that delivers a response signal to the first and second arbiters based on information stored in the first and second latch circuits.
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公开(公告)号:US20230125421A1
公开(公告)日:2023-04-27
申请号:US17893815
申请日:2022-08-23
Inventor: Tae Wook KANG , Sung Eun KIM , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE
Abstract: Disclosed is operation method of an encoder that receives a continuous time-series signal and respectively transmits first to N-th input signals to first to N-th input neuron circuits of spike neural network circuit. The method of operating the encoder includes receiving the continuous time-series signal, generating a plurality of discrete quantum signals by sampling and quantizing the continuous time-series signal, selecting first to N-th discrete quantum signals among the plurality of discrete quantum signals, matching the selected first to N-th discrete quantum signals with the first to N-th input neuron circuits, respectively, identifying discrete quantum signals, each of which has a quantum level different from a quantum level of a previous discrete quantum signal, from among the second to N-th discrete quantum signals, and activating the input signals to be transmitted to the input neuron circuits corresponding to the identified discrete quantum signals and the first discrete quantum signal.
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公开(公告)号:US20220413544A1
公开(公告)日:2022-12-29
申请号:US17847636
申请日:2022-06-23
Inventor: Kyuseung HAN , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Hyung-IL PARK , Kwang IL OH , Jae-Jin LEE
Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.
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