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公开(公告)号：US20230306247A1
公开(公告)日：2023-09-28
申请号：US18073830
申请日：2022-12-02
Inventor： In San JEON , Hyuk KIM , Jae-Jin LEE , Tae Wook KANG , Sung Eun KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH
Abstract: Disclosed is a neuron circuit, which includes a first bias circuit that adds a bias current to an input current to generate a biased input current, a logarithm-based neuron calculation circuit that performs a logarithm calculation on an amount of current of the biased input current to generate an input logarithm value and generates a biased output voltage by performing a logarithm-based Hodgkin-Huxley model calculation based on the input logarithm value, and a second bias circuit that adds a bias voltage to the biased output voltage to generate an output voltage.
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公开(公告)号：US20230140256A1
公开(公告)日：2023-05-04
申请号：US17965393
申请日：2022-10-13
Inventor： Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In San JEON
Abstract: Disclosed is an electronic device that supports a neural network including a neuron array including neurons, a row address encoder that receives spike signals from neurons and outputs request signals in response to the received spike signals, and a row arbiter tree that receives request signals from the row address encoder and outputs response signals in response to the received request signals. The row arbiter tree includes a first arbiter that arbitrates first and second request signals among request signals, a first latch circuit that stores a state of the first arbiter, a second arbiter that arbitrates third and fourth request signals among request signals, a second latch circuit that stores a state of the second arbiter, and a third arbiter that delivers a response signal to the first and second arbiters based on information stored in the first and second latch circuits.
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公开(公告)号：US20230125421A1
公开(公告)日：2023-04-27
申请号：US17893815
申请日：2022-08-23
Inventor： Tae Wook KANG , Sung Eun KIM , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE
Abstract: Disclosed is operation method of an encoder that receives a continuous time-series signal and respectively transmits first to N-th input signals to first to N-th input neuron circuits of spike neural network circuit. The method of operating the encoder includes receiving the continuous time-series signal, generating a plurality of discrete quantum signals by sampling and quantizing the continuous time-series signal, selecting first to N-th discrete quantum signals among the plurality of discrete quantum signals, matching the selected first to N-th discrete quantum signals with the first to N-th input neuron circuits, respectively, identifying discrete quantum signals, each of which has a quantum level different from a quantum level of a previous discrete quantum signal, from among the second to N-th discrete quantum signals, and activating the input signals to be transmitted to the input neuron circuits corresponding to the identified discrete quantum signals and the first discrete quantum signal.
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公开(公告)号：US20220309326A1
公开(公告)日：2022-09-29
申请号：US17550530
申请日：2021-12-14
Inventor： Tae Wook KANG , Sung Eun KIM , Kwang IL OH , Jae-Jin LEE , Hyuk KIM , Hyung-IL PARK , Kyung Jin BYUN
Abstract: Disclosed is a learning method of a neural network which includes a first intermediate neuron layer and a second intermediate neuron layer. The method includes performing first learning, which is based on a first synaptic weight layer, with respect to input subjects and the first intermediate neuron layer, determining intermediate neurons, which will perform second learning, from among intermediate neurons of the first intermediate neuron layer, based on the number of spikes of each of spike output signals of the intermediate neurons of the first intermediate neuron layer, and performing the second learning, which is based on a second synaptic weight layer, with respect to the intermediate neurons determined to perform the second learning.
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公开(公告)号：US20220201611A1
公开(公告)日：2022-06-23
申请号：US17552766
申请日：2021-12-16
Inventor： Hyuk KIM , HYUNG-IL PARK , Tae Wook KANG , Sung Eun KIM , Mi Jeong PARK , Kyung Jin BYUN , KWANG IL OH , Sukho LEE , Jae-Jin LEE , In Gi LIM , Kyuseung HAN
Abstract: Disclosed is an operating method of a user communication device, which includes receiving a wakeup signal from a stationary communication device over a first human body communication channel, the wakeup signal having a frequency in a low frequency band, switching from a standby mode to a wakeup mode in response to the wakeup signal, and receiving a data signal from the stationary communication device over the first human body communication channel during the wakeup mode, and the first human body communication channel is provided by a body of a user of the user communication device.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200234635A1
公开(公告)日：2020-07-23
申请号：US16838629
申请日：2020-04-02
Inventor： Woo Joo LEE , Suk Ho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: G09G3/3208 , H05B45/00 , H05B45/37 , G09G3/20 , G06F3/14 , G06F1/3218
Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.
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公开(公告)号：US20200067516A1
公开(公告)日：2020-02-27
申请号：US16542469
申请日：2019-08-16
Inventor： KWANG IL OH , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
IPC: H03L7/093
Abstract: The inventive concept includes an oscillating circuit, a phase inverting circuit, and a phase detecting circuit. The oscillating circuit generates a first clock to be used to sample an input signal. The phase inverting circuit outputs a second clock based on the first clock. The phase detecting circuit generates a control signal having a first logic value when a phase difference between a phase of the input signal and a phase of the second clock is less than a reference value for a reference time or more. The phase detecting circuit generates the control signal having a second logic value when the phase difference is equal to or greater than the reference value or when the phase difference is less than the reference value for a time shorter than the reference time. The phase inverting circuit inverts the phase of the second clock when a logic value of the control signal changes from the first logic value to the second logic value or when a logic value of the control signal changes from the second logic value to the first logic value.
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公开(公告)号：US20240104962A1
公开(公告)日：2024-03-28
申请号：US18340686
申请日：2023-06-23
Inventor： Tae Wook KANG , Sung Eun KIM , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE
CPC classification number: G06V40/40 , G06V10/70 , G06V40/1306
Abstract: Disclosed are a fingerprint forgery detection device and a method of operating the same. The fingerprint forgery detection device includes a memory that stores a first feature signal including biological channel feature information of a user, a transmitter including at least one transmission electrode for transmitting a pulse signal to the user, a receiver including at least one reception electrode for receiving a biological channel response signal in response to the transmitted pulse signal, and a signal processor for processing the biological channel response signal to detect whether a fingerprint is forged, and at least one processor that controls the memory, the transmitter, and the receiver.
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公开(公告)号：US20230289582A1
公开(公告)日：2023-09-14
申请号：US18084234
申请日：2022-12-19
Inventor： Young Hwan BAE , Jae-Jin LEE , Tae Wook KANG , Sung Eun KIM , Kyung Jin BYUN , Kwang IL OH , In San JEON
Abstract: A neuron circuit including a first internal circuit that receives a plurality of spike input signals, generates a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and outputs a second sum value by adding a membrane potential value to the first sum value, a spike generating circuit that generates a spike output signal, a membrane potential generating circuit that generates the membrane potential value, a second internal circuit that counts a last spike time based on the spike output signal, and an online learning circuit that receives a last input time from the first internal circuit and performs LTP learning based on the last input time or receives the last spike time from the second internal circuit and performs LTD learning based on the last spike time.
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公开(公告)号：US20200315438A1
公开(公告)日：2020-10-08
申请号：US16842497
申请日：2020-04-07
Inventor： Kwang IL OH , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
Abstract: A capsule endoscope image receiver includes a receiving electrode unit that receives first and second differential signals from a capsule endoscope image transmitter through a human body communication channel, an analog amplifying unit that receives the first and second differential signals and outputs first and second amplified differential signals, and a signal restoring unit that receives the first and second amplified differential signals and restores image information. The analog amplifying unit includes a first amplifier that outputs the first amplified differential signal, a second amplifier that outputs the second amplified differential signal, and an input impedance that is connected between a first inverting input terminal of the first amplifier and a second inverting input terminal of the second amplifier and obtains a gain of differential signal amplification in which a high frequency component of the first and second amplified differential signals is greater than a low frequency component.
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