公开(公告)号：US07360050B2

公开(公告)日：2008-04-15

申请号：US11681375

申请日：2007-03-02

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

摘要翻译： 集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。 器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。 在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。 在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

公开(公告)号：US20120173810A1

公开(公告)日：2012-07-05

申请号：US13421701

申请日：2012-03-15

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

摘要翻译： 一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址 以指示要写入第一数据的DRAM中的存储器核的列位置。 该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。 如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。 接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

公开(公告)号：US20100332719A1

公开(公告)日：2010-12-30

申请号：US12875483

申请日：2010-09-03

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarre ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarre ,  David Nguyen

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

摘要翻译： 在控制存储器件的方法中，以下是通过第一组互连资源传送的：指定一行存储器单元的激活的第一命令; 指定写操作的第二命令，其中写数据被写入行; 指定在写入数据写入之后是否发生预充电的一点; 以及指定是否将为写入操作发布数据掩码信息的代码。 如果代码指定信息将被发出，则在传送代码之后，通过第一组互连资源传送指定是否选择性地写入写入数据的部分的信息。 要写入与写入操作相关的写入数据通过与第一组互连资源分开的第二组互连资源传送。

公开(公告)号：US06310814B1

公开(公告)日：2001-10-30

申请号：US09637892

申请日：2000-08-08

申请人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

发明人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.

摘要翻译： 一种用于在动态随机存取存储器（DRAM）组件中同时刷新第一和第二行存储器单元的装置和方法，所述动态随机存取存储器（DRAM）组件包括以行为单位组织的多组存储器单元。 DRAM组件中的命令接口接收激活请求和预充电请求。 DRAM组件中的行寄存器表示DRAM组件中的一行。 DRAM组件中的逻辑响应于激活请求而激活由行寄存器指示的行，并且响应于预充电请求预先充电该行，该行位于由激活请求指示的存储体中以及通过预充电请求。

公开(公告)号：US6075730A

公开(公告)日：2000-06-13

申请号：US169729

申请日：1998-10-09

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/229

摘要： A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

摘要翻译： 存储器件包括具有控制引脚和双向数据引脚的互连。 内存核心存储数据。 存储器接口电路连接到互连和存储器核。 存储器接口电路包括延迟电路，以在存储器核心写入事务期间建立写入延迟，使得存储器核心写入事务具有基本上等同于存储器核心读取事务的处理时间。 延迟电路将存储器核心写入事务延迟一段时间，该时间对应于信号在互连上行进所需的时间。

公开(公告)号：US08205056B2

公开(公告)日：2012-06-19

申请号：US13230741

申请日：2011-09-12

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

摘要翻译： 存储器控制器具有在第一组互连资源上传送指定激活一行存储器单元的第一命令的接口，指定针对存储器单元行的写操作的第二命令，指定 是否与写入操作相关地进行预充电，指定是否将与写入操作相关联地发布数据掩码信息的代码，以及如果代码指定将发出数据掩码信息的数据掩码信息，指定是否选择性地 写入与写入操作相关联的写入数据的部分。 存储器控制器接口还通过第二组互连资源与第一组互连资源（写入数据）分离。

公开(公告)号：US20090129178A1

公开(公告)日：2009-05-21

申请号：US12349485

申请日：2009-01-06

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G11C11/416

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.

摘要翻译： 集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。 指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

公开(公告)号：US07330953B2

公开(公告)日：2008-02-12

申请号：US11692162

申请日：2007-03-27

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

摘要翻译： 存储器系统具有第一，第二和第三互连以及耦合到互连的集成电路存储器件。 第二个互连传送写入命令和读取命令。 第三个互连传送写入数据和读取数据。 集成电路存储器件包括耦合到第一互连的引脚以接收时钟信号。 存储器件还包括耦合到第二互连以接收写入命令和读取命令的第一多个引脚，以及耦合到第三互连以接收写入数据和断言读取数据的第二多个引脚。 应用控制信息以在从接收到写入命令之后发生第一预定延迟时间之后启动写入操作。 在时钟信号的时钟周期期间，第二多个引脚的每个引脚传送两位读取数据。

公开(公告)号：US07330952B2

公开(公告)日：2008-02-12

申请号：US11692159

申请日：2007-03-27

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

摘要翻译： 集成电路存储器件包括第一组引脚和存储器核。 第一组引脚使用时钟信号接收写入命令和读取命令。 控制信息在接收到写入命令之后经过预定的延迟时间之后响应于写入命令被发出，该控制信息在存储器件中启动写入操作。 第二组引脚在从接收到读命令之后发生第一延迟时间后输出读数据。 第二组引脚的每个引脚在时钟信号的时钟周期期间输出两位读取数据。 第二组引脚还在接收到写入命令之后延迟了第二个延迟时间之后也接收到写入数据。 第二延迟时间基于第一延迟时间。

公开(公告)号：US07287119B2

公开(公告)日：2007-10-23

申请号：US11681384

申请日：2007-03-02

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.

摘要翻译： 具有延迟写入命令处理的集成电路存储器件包括耦合到存储器核心的第一组引脚，第一组引脚以接收列地址的行地址。 耦合到存储器核心的第二组引脚用于接收感测命令，后接写入命令。 感测命令指定感测由行地址识别的一行存储器单元，并且写入命令指定存储器件接收写入数据并将写入数据存储在由列地址标识的列位置处。 在从第二组引脚接收到写命令之后第一个延迟发生之后，写入命令在内部发布到存储器件中。