公开(公告)号：US08504790B2

公开(公告)日：2013-08-06

申请号：US13424273

申请日：2012-03-19

申请人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

发明人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

IPC分类号： G06F12/00

CPC分类号： G11C7/1006 ,  G06F13/1626 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2218 ,  G11C2207/229

摘要： A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

摘要翻译： 存储器控制器芯片执行用于将数据存储在包括具有动态随机存取存储单元的存储器核心的存储器芯片中的方法。 该方法包括向存储器芯片的第一接口发送写命令，其中写命令指定写操作。 在发送写命令之后，存储器控制器芯片等待与由存储芯片存储写入命令的时间段对应的第一时间段，并且将与写入操作相关联的数据发送到存储器芯片的第二接口， 其中所述数据的发送在第二时间段之后发生，在所述第一时间段之后的所述第二时间段，使得发送所述写入命令并发送所述数据被隔开第一预定延迟时间，所述第一预定延迟时间包括所述第一时间段和 第二个时期。

公开(公告)号：US08243533B2

公开(公告)日：2012-08-14

申请号：US12648579

申请日：2009-12-29

申请人： Kie-Bong Ku

发明人： Kie-Bong Ku

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C2207/2218

摘要： A semiconductor memory device allows a read command to be inputted thereto after a passage of a relatively short time period from a point in time where a write command has been inputted thereto. A method of operating the semiconductor memory device includes inputting a write command, inputting a read command in a preset period of time after the write command has been inputted, loading read data of a memory cell onto a data bus in response to the read command; and loading write data from outside of the semiconductor memory device onto the data bus in response to the write command.

摘要翻译： 半导体存储器件允许在从输入写入命令的时间点相对较短的时间段过去之后输入读取命令。 一种操作半导体存储器件的方法包括：输入写入命令，在输入写入命令之后的预定时间段内输入读取命令，响应读取命令将存储器单元的读取数据加载到数据总线上; 以及响应写入命令将写入数据从半导体存储器件外部加载到数据总线上。

公开(公告)号：US20120179866A1

公开(公告)日：2012-07-12

申请号：US13424273

申请日：2012-03-19

申请人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

发明人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

IPC分类号： G06F12/02

CPC分类号： G11C7/1006 ,  G06F13/1626 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2218 ,  G11C2207/229

摘要： A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

摘要翻译： 存储器控制器芯片执行用于将数据存储在包括具有动态随机存取存储单元的存储器核心的存储器芯片中的方法。 该方法包括向存储器芯片的第一接口发送写命令，其中写命令指定写操作。 在发送写命令之后，存储器控制器芯片等待与由存储芯片存储写入命令的时间段对应的第一时间段，并且将与写入操作相关联的数据发送到存储器芯片的第二接口， 其中所述数据的发送在第二时间段之后发生，在所述第一时间段之后的所述第二时间段，使得发送所述写入命令并发送所述数据被隔开第一预定延迟时间，所述第一预定延迟时间包括所述第一时间段和 第二个时期。

公开(公告)号：US07843742B2

公开(公告)日：2010-11-30

申请号：US11996544

申请日：2006-07-26

申请人： Toshio Sunaga ,  Norio Fujita

发明人： Toshio Sunaga ,  Norio Fujita

IPC分类号： G11C7/10

CPC分类号： G11C7/22 ,  G11C8/10 ,  G11C11/4076 ,  G11C2207/2218

摘要： The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.

摘要翻译： 本发明涉及包括存储单元阵列并连接到地址输入，命令输入和数据输入/输出的存储器系统，所述存储器系统包括用于锁存读取地址的锁存电路（RALTH和WALTH）和 写地址从地址输入输入，地址选择电路（ACOMSEL），用于选择锁存在锁存电路中的读地址和写地址中的任何一个作为访问地址，用于锁存的读锁存电路（PFLTH） 从存储单元阵列读取的读取数据，用于锁存从数据输入/输出输入的写入数据的写入锁存电路（DINLTH）和用于控制由所述地址选择电路选择的存取地址的控制电路（ACTL） 响应于从所述命令输入输入的命令，所述控制电路用于控制与所选择的访问地址对应的存储单元是否被激活，并且进一步选择所述ac 写入地址是写入地址，写入被写入锁存电路的写入数据写入激活的存储单元的定时。

公开(公告)号：US07793039B2

公开(公告)日：2010-09-07

申请号：US12349485

申请日：2009-01-06

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

摘要翻译： 半导体存储器件包括存储器核，从第一组互连资源接收写数据的第一接口和与第一接口分开的第二接口，以从第二组互连资源接收列地址和第一 码。 列地址与写入数据相关联，并标识存储写入数据的存储器核心的列。 第一代码指示写数据是否被数据掩码信息选择性地屏蔽。 如果第一代码指示写入数据被选择性地屏蔽，则第二接口将接收指定是否选择性地将写数据的部分写入存储器核的数据掩码信息。

公开(公告)号：US20100142248A1

公开(公告)日：2010-06-10

申请号：US12657385

申请日：2010-01-19

申请人： Robert Norman

发明人： Robert Norman

IPC分类号： G11C5/02 ,  G11C7/10

CPC分类号： G11C7/1006 ,  G06F13/1668 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1096 ,  G11C2207/2218

摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

公开(公告)号：US07649788B2

公开(公告)日：2010-01-19

申请号：US12006970

申请日：2008-01-08

申请人： Robert Norman

发明人： Robert Norman

IPC分类号： G11C11/00

CPC分类号： G11C7/1006 ,  G06F13/1668 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1096 ,  G11C2207/2218

摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

摘要翻译： 本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。 在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。 例如，集成电路可以包括设置在多层存储器中的存储单元。 在一个实施例中，存储器单元可以是第三维存储器单元。 集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。 在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。 每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

公开(公告)号：US07068566B2

公开(公告)日：2006-06-27

申请号：US10834173

申请日：2004-04-29

申请人： Eitaro Otsuka ,  Koichi Mizugaki

发明人： Eitaro Otsuka ,  Koichi Mizugaki

IPC分类号： G11C8/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2218 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2211/4061

摘要： The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write request regarding a first data group is issued, a write operation of the first data group for a first group of memory cells among a set of memory cells selected by the current address is executed. When this occurs, a read operation of a second data group for a second group of memory cells among the set of memory cells is executed on a preliminary basis. The second group of memory cells is different from the first group of memory cells. In a second situation in which a read request for the second data group is issued while the current address is being maintained, the second data group that has been read preliminarily and held is externally output without executing a read operation for the second group of memory cells.

摘要翻译： 本发明提供了如果发出不伴随地址改变的读取请求，则使半导体器件输出数据的技术。 在发出关于第一数据组的写请求的第一种情况下，执行由当前地址选择的一组存储单元中的第一组存储单元的第一数据组的写操作。 当发生这种情况时，初步地执行存储器单元组中的第二组存储器单元的第二数据组的读取操作。 第二组存储器单元与第一组存储器单元不同。 在维持当前地址时发出对第二数据组的读取请求的第二种情况下，已经预先和保持读取的第二数据组被外部输出，而不执行第二组存储器单元的读取操作 。

公开(公告)号：US07031201B2

公开(公告)日：2006-04-18

申请号：US11005544

申请日：2004-12-06

申请人： Sung-Ryul Kim ,  Dae-Hee Jung

发明人： Sung-Ryul Kim ,  Dae-Hee Jung

IPC分类号： G11C7/00

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/413 ,  G11C2207/107 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.

摘要翻译： 集成电路存储器件包括存储单元阵列，被配置为将数据传送到存储单元阵列的多条数据输入线以及被配置为从存储单元阵列传送数据的多条数据输出线。 该装置还包括存储器写入缓冲器，其接收存储单元阵列的写入数据并且响应地驱动数据输入线，读出放大器和多个读出放大器输入线，其被配置为将数据传送到读出放大器。 该装置还包括耦合到数据输入线，数据输出线和读出放大器输入线的选择电路，并且被配置成响应于控制信号将数据输入线选择性地耦合到读出放大器输入线。

公开(公告)号：US06937503B2

公开(公告)日：2005-08-30

申请号：US10892522

申请日：2004-07-14

申请人： Jeong-Duk Sohn

发明人： Jeong-Duk Sohn

IPC分类号： G11C11/24 ,  G11C11/406 ,  H01L20060101

CPC分类号： G11C8/08 ,  G11C7/1021 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2207/2218 ,  G11C2211/4065

摘要： Memory circuits and methods are described providing an interface with high density dynamic memory (DRAM), such 1T1C (1 transistor and 1 capacitor) memory cells, providing full compatibility with static memory (SRAM). The circuitry overcomes the shortcomings with DRAM, such as associated with the restore and refresh operations, which have prevented full utilization of DRAM cores with SRAM compatible devices. The circuit can incorporate a number of inventive aspects, either singly or more preferably in combination, including a pulsed word line structure for limiting the maximum page mode cycle time, an address duration compare function with optional address buffering, and a late write function wherein the write operation commences after the write control signals are disabled.

摘要翻译： 描述了提供具有高密度动态存储器（DRAM）的接口的存储器电路和方法，例如提供与静态存储器（SRAM）的完全兼容性的1T1C（1晶体管和1电容器）存储器单元。 该电路克服了DRAM的缺点，例如与恢复和刷新操作相关联，这阻止了使用SRAM兼容设备的DRAM内核的充分利用。 该电路可以单独地或更优选组合地并入多个创造性方面，包括用于限制最大页面模式周期时间的脉冲字线结构，具有可选地址缓冲的地址持续时间比较功能和后期写入功能，其中， 写操作在禁止写控制信号后开始。