公开(公告)号：US20070088938A1

公开(公告)日：2007-04-19

申请号：US11253906

申请日：2005-10-18

申请人： Lucian Codrescu ,  William Anderson

发明人： Lucian Codrescu ,  William Anderson

IPC分类号： G06F7/38

CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/3851

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）处理通信（例如，CDMA）系统中的传输。 所公开的方法和系统过程在多线程处理器中产生的中断通过在中断寄存器中接收到统计不确定的中断类型的多个中断，然后将多个处理线程与中断寄存器相关联，以从中断寄存器接收中断。 所述方法和系统掩蔽所述多个处理线程的至少一个子集，以便在所述子集内的每个所述线程内接收一个或多个预定类型的所述多个中断中的一个，从而在每个线程的基础上控制所述处理 根据与特定线程相关联的掩码的多个中断。

公开(公告)号：US20060294341A1

公开(公告)日：2006-12-28

申请号：US11165757

申请日：2005-06-23

申请人： Erich Plondke ,  William Anderson ,  Lucian Codrescu

发明人： Erich Plondke ,  William Anderson ,  Lucian Codrescu

IPC分类号： G06F12/00

CPC分类号： G06F9/4812 ,  G06F12/1027 ,  Y02D10/13 ,  Y02D10/24

摘要： A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.

摘要翻译： 共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新​​启用异常和可选中断，解决原因 异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。

公开(公告)号：US20060242384A1

公开(公告)日：2006-10-26

申请号：US11115916

申请日：2005-04-26

申请人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

发明人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

IPC分类号： G06F15/00

CPC分类号： G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

公开(公告)号：US20060230253A1

公开(公告)日：2006-10-12

申请号：US11103744

申请日：2005-04-11

申请人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

发明人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

IPC分类号： G06F15/00

CPC分类号： H04M1/72522 ,  G06F9/3012 ,  G06F9/3885 ,  H04M1/2535 ,  H04M2250/02

摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.

摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 音序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

公开(公告)号：US20060218559A1

公开(公告)日：2006-09-28

申请号：US11089474

申请日：2005-03-23

申请人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

发明人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

IPC分类号： G06F9/46

CPC分类号： G06F9/3851

摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

公开(公告)号：US20060212681A1

公开(公告)日：2006-09-21

申请号：US11086475

申请日：2005-03-21

申请人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Sujat Jamil ,  William Anderson

发明人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Sujat Jamil ,  William Anderson

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3851 ,  G06F9/3853

摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

公开(公告)号：US10289412B2

公开(公告)日：2019-05-14

申请号：US13369693

申请日：2012-02-09

申请人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Swaminathan Balasubramanian

发明人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Swaminathan Balasubramanian

IPC分类号： G06F9/30

摘要： Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.

公开(公告)号：US10120692B2

公开(公告)日：2018-11-06

申请号：US13192916

申请日：2011-07-28

申请人： Sergei Larin ,  Lucian Codrescu ,  Anshuman Das Gupta

发明人： Sergei Larin ,  Lucian Codrescu ,  Anshuman Das Gupta

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30178 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3853

摘要： A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.

公开(公告)号：US10025711B2

公开(公告)日：2018-07-17

申请号：US13470643

申请日：2012-05-14

申请人： Peter G. Sassone ,  Christopher Edward Koob ,  Dana M. Vantrease ,  Suresh K. Venkumahanti ,  Lucian Codrescu

发明人： Peter G. Sassone ,  Christopher Edward Koob ,  Dana M. Vantrease ,  Suresh K. Venkumahanti ,  Lucian Codrescu

IPC分类号： G06F13/00 ,  G06F12/0804 ,  G06F1/32 ,  G06F12/0806 ,  G06F12/0846

摘要： Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

公开(公告)号：US09207943B2

公开(公告)日：2015-12-08

申请号：US12405271

申请日：2009-03-17

申请人： Erich James Plondke ,  Lucian Codrescu

发明人： Erich James Plondke ,  Lucian Codrescu

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F9/3851 ,  G06F9/4812 ,  G06F9/4881

摘要： In a particular embodiment, a method is disclosed that includes receiving an interrupt at a first thread, the first thread including a lowest priority thread of a plurality of executing threads at a processor at a first time. The method also includes identifying a second thread, the second thread including a lowest priority thread of a plurality of executing threads at a processor at a second time. The method further includes directing a subsequent interrupt to the second thread.

摘要翻译： 在特定实施例中，公开了一种包括在第一线程处接收中断的方法，所述第一线程在第一时间包括处理器处的多个执行线程的最低优先级线程。 所述方法还包括识别第二线程，所述第二线程在第二时间包括处理器处的多个执行线程的最低优先级线程。 该方法还包括将后续中断引导到第二线程。