公开(公告)号：US06830984B2

公开(公告)日：2004-12-14

申请号：US10078233

申请日：2002-02-15

申请人： Richard T. Schultz ,  Peter J. Wright

发明人： Richard T. Schultz ,  Peter J. Wright

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

摘要翻译： 集成电路中的多个镶嵌层可以形成若干有利的设计或组件，这些设计或组件可以降低成本或提高某些设计的性能。 在电力总线信号的实施例中，可以使用多个镶嵌层来形成具有增加的功率容量和较低成本的迹线。 在其他实施例中，可以使用多个镶嵌层来形成具有增加的性能的诸如电容器和电感器的部件。

公开(公告)号：US06675139B1

公开(公告)日：2004-01-06

申请号：US09268867

申请日：1999-03-16

申请人： Mark W. Jetton ,  Richard A. Laubhan ,  Richard T. Schultz

发明人： Mark W. Jetton ,  Richard A. Laubhan ,  Richard T. Schultz

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems. A netlist of a circuit design receiving power from the power-bus grid can be created after the floor plan design is analyzed and completed. The circuit design can be simulated and layout tools can map the circuit design structures along the power-bus grid wires according to the floor plan design. A back annotated netist can be generated and simulated to verify the circuit design's operation.

摘要翻译： 一种用于设计和映射集成电路中的电力总线电网的方法。 通过将电力总线电网的线段映射到IC芯的各种金属层来创建平面图。 指定模拟，数字和存储器区域的电流消耗的功率区也映射到IC内核。 生成和模拟平面图设计的网表，模拟返回电流密度和相对于电源区域的电线段中的电压降值。 使用颜色图分析计算的电流密度和电压降值，以指示电线段的电流密度和电压降水平。 电源总线线段的颜色与颜色图中的电流密度和电压降水平相符合显示，有助于设计人员识别潜在的电迁移和电压降问题。 如果计算的密度和电压降值表示潜在的电迁移或电压降问题，则可以修改平面图设计。在分析和完成平面图设计后，可以创建从电力总线电网接收电力的电路设计的网表。 电路设计可以模拟，布局工具可以根据平面图设计将电路设计结构沿着电力总线网格线进行映射。 可以生成和模拟背面注释的网络主题以验证电路设计的操作。

公开(公告)号：US06408265B1

公开(公告)日：2002-06-18

申请号：US09233529

申请日：1999-01-20

申请人： Richard T. Schultz ,  Kevin J. Gearhardt

发明人： Richard T. Schultz ,  Kevin J. Gearhardt

IPC分类号： G06F945

CPC分类号： G06F17/5022

摘要： A metastability risk simulation analysis device and method for identifying metastability risks of a design. The metastability risk simulation analysis device includes computer readable code which is configured to analyze simulation information relating to the design and determine whether the design presents a metastability risk. Desirably, the computer readable code is configured to determine whether two signals, such as a data signal and a clock signal of a synchronous element of the design, cross over each other thereby presenting a metastability risk, and is configured to generate a summary report identifying those synchronous elements of the design which present a metastability risk. Preferably, the computer readable code is configured to analyze simulation information relating to best case and worst case simulations of the design, and is configured to scan the simulation information to identify an edge of a clock signal and an edge of a data signal of the best case and worst case simulations and determine whether the signals cross each other.

摘要翻译： 一种用于识别设计的亚稳态风险的亚稳态风险模拟分析装置和方法。 亚稳态风险模拟分析装置包括计算机可读代码，其被配置为分析与设计有关的模拟信息，并确定设计是否呈现亚稳态风险。 期望地，计算机可读代码被配置为确定诸如设计的同步元件的数据信号和时钟信号的两个信号是否相互交叉从而呈现亚稳定性风险，并且被配置为生成识别 那些呈现亚稳态风险的设计的同步元件。 优选地，计算机可读代码被配置为分析与设计的最佳情况和最坏情况模拟相关的模拟信息，并且被配置为扫描模拟信息以识别时钟信号的边缘和最佳数据信号的边缘 情况和最坏情况模拟，并确定信号是否交叉。

公开(公告)号：US06346721B1

公开(公告)日：2002-02-12

申请号：US09804118

申请日：2001-03-12

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L2710

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid electrically coupled to the plurality of circuits. The power bus grid is formed of a plurality of power bus straps having a strap density that progressively varies with distance from the geometric center toward the periphery.

摘要翻译： 集成电路包括具有周边和几何中心的半导体材料的衬底，形成在衬底上的多个电路，以及电耦合到多个电路的电力总线栅极。 电力总线栅格由多个电源母线带形成，带子密度随着几何中心向周边的距离而逐渐变化。

公开(公告)号：US06340905B1

公开(公告)日：2002-01-22

申请号：US09596677

申请日：2000-06-19

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop, such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals. After a predetermined number of adjustment cycles, the overall clock skew is minimized by repeated adjustments.

摘要翻译： 时钟树去偏置电路动态地最小化同步集成电路的同步电路组件的操作的时钟信号的偏移。 时钟树偏移电路在一段时间内以重复的间隔减少时钟树的偏斜。 然后关闭时钟树偏移电路，以防止对时钟信号进行不必要的进一步调整，但是当条件改变时可以重新启动时钟树偏移。 时钟信号以连续的环路配对在一起，使得当与下一个时钟信号配对时，每个时钟信号是该对的第一个时钟信号，并且当与之前的时钟信号配对时是第二个时钟信号。 时钟树偏移电路检测每对时钟信号之间的绝对偏差。 时钟树偏移电路调整每对的第一个时钟信号朝向该对的第二个时钟信号，以减少两个时钟信号之间的偏差。 在预定数量的调整周期之后，通过重复调整来最小化整个时钟偏移。

公开(公告)号：US5999029A

公开(公告)日：1999-12-07

申请号：US671862

申请日：1996-06-28

申请人： Hoang P. Nguyen ,  Richard T. Schultz

发明人： Hoang P. Nguyen ,  Richard T. Schultz

IPC分类号： H03K3/037

CPC分类号： H03K3/0375

摘要： A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.

摘要翻译： 降低亚稳态影响的元硬化电路优选地包括脉冲发生器，其被耦合以接收第一时钟信号并响应于此产生第二时钟信号和使能信号。 耦合优选三态的缓冲器以接收第一数据信号和使能信号，并响应于此产生第二数据信号。 诸如触发器的双稳态器件被耦合以接收第二时钟信号和第二数据信号。 脉冲发生器优选地包括组合装置和延迟装置。 缓冲器优选地包括至少一个三态反相器和保持器电路。 降低亚稳效应的方法优选地包括产生第二数据输入信号和大于第一数据输入信号和第一时钟信号之间的延迟的第二时钟信号之间的延迟的步骤。 优选的发生步骤在一个时钟周期内发生。 该方法还优选地包括通过响应于第一时钟信号产生第二时钟信号并组合第一和第二时钟信号以产生使能信号来产生使能脉冲，以及响应于第一数据输入产生第二数据输入信号 信号，其中产生所述第二数据输入信号包括接收使能信号。 该方法优选地包括响应于第二数据输入信号和第二时钟信号产生输出信号的步骤，输出信号具有降低的亚稳效应。