公开(公告)号：US06830984B2

公开(公告)日：2004-12-14

申请号：US10078233

申请日：2002-02-15

申请人： Richard T. Schultz ,  Peter J. Wright

发明人： Richard T. Schultz ,  Peter J. Wright

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

摘要翻译： 集成电路中的多个镶嵌层可以形成若干有利的设计或组件，这些设计或组件可以降低成本或提高某些设计的性能。 在电力总线信号的实施例中，可以使用多个镶嵌层来形成具有增加的功率容量和较低成本的迹线。 在其他实施例中，可以使用多个镶嵌层来形成具有增加的性能的诸如电容器和电感器的部件。

公开(公告)号：US08564030B2

公开(公告)日：2013-10-22

申请号：US13157411

申请日：2011-06-10

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/66545

摘要： A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.

摘要翻译： 半导体器件制造工艺包括在半导体衬底上的一个或多个替代金属栅极上形成绝缘心轴。 心轴包括第一绝缘材料。 每个心轴具有与其底部浇口大致相同的宽度，每个心轴至少与其下面的浇口一样宽。 在每个绝缘心轴周围形成心轴间隔物。 心轴间隔件包括第一绝缘材料。 每个心轴间隔件具有从底部变宽到顶部较窄的轮廓。 第二绝缘材料的第二绝缘层形成在晶体管的上方。 通过从心轴之间的晶体管的部分去除第二绝缘材料来形成到栅极的源极和漏极的沟槽。 通过在第一沟槽中沉积导电材料来形成与栅极的源极和漏极的沟槽接触。

公开(公告)号：US08076236B2

公开(公告)日：2011-12-13

申请号：US12475989

申请日：2009-06-01

申请人： Richard T. Schultz ,  Donald R. Weiss

发明人： Richard T. Schultz ,  Donald R. Weiss

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

摘要翻译： 通过提供双向，自对准局部互连的技术，通过在未连接到局部互连的栅极的部分上采用栅极硬掩模，技术来形成改进的SRAM，从而显着减少与栅极短路的局部互连。 实施例包括在栅极上形成栅极硬掩模，形成覆盖栅极电极和有源硅区域的部分的双向沟槽，蚀刻硬掩模层以暴露栅极电极连接到局部互连的区域，以及用导电 材料以形成自对准局部互连。

公开(公告)号：US07818157B2

公开(公告)日：2010-10-19

申请号：US10174681

申请日：2002-06-19

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/44 ,  G06F9/455 ,  H03K19/00

CPC分类号： G06F17/5036

摘要： A method for analyzing an electrical characteristic of wire segments configured as one or more power meshes in an integrated circuit (IC) core comprising the steps of (A) specifying design information corresponding to the power meshes, (B) specifying at least one type of analysis to be performed, where the analysis comprises (i) generating a file corresponding to the IC core in a format compatible with an electronic circuit simulator and (ii) calculating the electrical characteristic of the wire segments via the circuit simulator, and (C) displaying the calculated electrical characteristic.

摘要翻译： 一种用于分析被配置为集成电路（IC）核心中的一个或多个电力网格的线段的电气特性的方法，包括以下步骤：（A）指定与所述电力网格对应的设计信息，（B）指定至少一种类型 要进行分析，其中分析包括（i）以与电子电路模拟器兼容的格式生成与IC芯相对应的文件，以及（ii）经由电路模拟器计算线段的电特性，以及（C） 显示计算的电气特性。

公开(公告)号：US07183791B2

公开(公告)日：2007-02-27

申请号：US10962262

申请日：2004-10-11

申请人： John D. Walker ,  SangJune Park ,  Richard T. Schultz

发明人： John D. Walker ,  SangJune Park ,  Richard T. Schultz

IPC分类号： G01R31/26

CPC分类号： G01R31/2642 ,  G01R31/2856 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.

摘要翻译： 提供了一种集成电路，其包括被测晶体管器件，AC驱动电路，AC偏置电路和DC偏置电路。 交流驱动电路产生交流驱动信号。 AC偏置电路响应于AC驱动信号在AC偏置条件下偏置晶体管器件。 直流偏置电路在直流偏置条件下偏置晶体管器件。 开关电路在AC应力模式下选择性地将晶体管器件耦合到AC偏置电路，并以DC测量模式将DC耦合到DC偏置电路。

公开(公告)号：US06442741B1

公开(公告)日：2002-08-27

申请号：US09680893

申请日：2000-10-06

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. Timing margin (set up and hold time) and signal skew (change in signal timing) are derived under best and worst case functional conditions by determining differences in the transition times of the predictive input waveforms for the cells of the logic cone.

摘要翻译： 通过使用传统的仿真，原理图和波形查看工具自动识别，跟踪和显示电路的相关逻辑单元和波形。 导出到每个逻辑单元的输入和输出波形以及每个波形的转换和转换时间点。 输出波形和所选择的转换时间点识别预测输入波形及其转换时间，这导致所选转换时间点的输出信号转换。 预测输入信号是前一预测逻辑单元的输出信号，由此识别先前的预测逻辑单元。 用每个新的识别的预测逻辑单元执行该过程的重复以自动导出单元的串联或逻辑锥。 通过确定逻辑锥的单元的预测输入波形的转换时间的差异，在最佳和最差情况下的功能条件下导出定时裕度（设置和保持时间）和信号偏移（信号时序的变化）。

公开(公告)号：US06433598B1

公开(公告)日：2002-08-13

申请号：US09915237

申请日：2001-07-25

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals. After a predetermined number of adjustment cycles, the overall clock skew is minimized by repeated adjustments.

摘要翻译： 时钟树去偏置电路动态地最小化同步集成电路的同步电路组件的操作的时钟信号的偏移。 时钟树偏移电路在一段时间内以重复的间隔减少时钟树的偏斜。 然后关闭时钟树偏移电路，以防止对时钟信号进行不必要的进一步调整，但是当条件改变时可以重新启动时钟树偏移。 时钟信号以连续环路配对在一起，使得当与下一个时钟信号配对时，每个时钟信号是该对的第一个时钟信号，并且当与之前的时钟信号配对时是第二个时钟信号。 时钟树偏移电路检测每对时钟信号之间的绝对偏差。 时钟树偏移电路调整每对的第一个时钟信号朝向该对的第二个时钟信号，以减少两个时钟信号之间的偏差。 在预定数量的调整周期之后，通过重复调整来最小化整个时钟偏移。

公开(公告)号：US06429714B1

公开(公告)日：2002-08-06

申请号：US10109974

申请日：2002-03-29

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H03K300

CPC分类号： G06F1/10

摘要： A multilevel clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. There are multiple temporary clock buffer signals at each level of the multilevel clock tree. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries at each level of the temporary clock buffer. The clock tree deskew circuit reduces the clock tree skew, on a level by level basis, in repeated intervals over a period of time. When each level of the tree deskew circuit is deskewed, that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock tree deskew circuit adjusts the variable delay clock buffer signal of each pair toward the temporary clock buffer signal of the pair to reduce the skew between the two clock buffer signals. After a predetermined number of adjustment cycles, the overall clock skew of the variable delay clock buffer signal is minimized by repeated adjustments. The variable delay clock buffer signals of each level may be optionally set as conditions warrant.

摘要翻译： 多电平时钟树在时钟树偏移电路中使用临时时钟缓冲器或参考信号来动态地最小化同步集成电路的同步电路部件的操作的可变延迟时钟信号中的偏移。 在多级时钟树的每个级别都有多个临时时钟缓冲信号。 通过在临时时钟缓冲器的每个级别提供相同的路径长度和路径几何形状来最小化临时时钟缓冲器信号之间的偏移。 时钟树偏移电路在一段时间内以重复的间隔逐级降低时钟树的偏移。 当每个级别的树偏移校正电路进行偏斜校正时，该时钟树偏移电路的电平然后被关闭，以防止对时钟信号的不必要的进一步调整，但是当条件改变时可以重新开启时钟树偏斜。 时钟树偏移电路将每对的可变延迟时钟缓冲器信号调整成对的临时时钟缓冲器信号，以减少两个时钟缓冲器信号之间的偏差。 在预定数量的调整周期之后，通过重复调整使可变延迟时钟缓冲信号的总体时钟偏移最小化。 每个级别的可变延迟时钟缓冲器信号可以可选地根据条件来设置。

公开(公告)号：US08716124B2

公开(公告)日：2014-05-06

申请号：US13295574

申请日：2011-11-14

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L21/4763

CPC分类号： H01L27/088 ,  H01L21/76801 ,  H01L21/76895 ,  H01L21/76897

摘要： A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

摘要翻译： 半导体器件制造工艺包括在半导体衬底上的替代金属栅极上形成绝缘心轴，其中第一栅极具有源极和漏极，并且至少一个第二栅极与第一栅极隔离。 在每个绝缘心轴周围形成心轴间隔物。 心轴和心轴间隔件包括第一绝缘材料。 第二绝缘材料的第二绝缘层形成在晶体管的上方。 通过去除绝缘心轴之间的第二绝缘材料，将一个或多个第一沟槽形成到第一栅极的源极和漏极。 通过去除第二栅极上方的第一绝缘材料和第二绝缘材料的部分，形成第二沟槽到第二栅极。 第一沟槽和第二沟槽填充有导电材料，以形成第一栅极的源极和漏极的第一接触以及到第二栅极的第二接触。

公开(公告)号：US20100304564A1

公开(公告)日：2010-12-02

申请号：US12475796

申请日：2009-06-01

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L21/3205

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475

摘要： A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.

摘要翻译： 半导体器件制造工艺包括使用硬掩模在半导体衬底上形成晶体管的栅极。 在门上的一个或多个选定区域中选择性地去除硬掩模。 在所选择的区域中去除硬掩模允许栅极通过位于晶体管基本上的至少一个绝缘层连接到上金属层。 导电材料沉积在通过至少一个绝缘层形成的一个或多个沟槽中。 导电材料在所选择的区域中的至少一个中形成与栅极的局部互连。