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31.发明授权Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests 失效总线接口状态机可独立访问内存，处理器和寄存器，用于并发处理不同类型的请求
公开(公告)号：US5471638A
公开(公告)日：1995-11-28
申请号：US263987
申请日：1994-06-22
申请人： James W. Keeley
发明人： James W. Keeley
摘要： A processor couples to a system bus and includes a high performance microprocessor which tightly couples to a local memory. The processor is organized at the interface level into a plurality of interface sections which include a corresponding number of state machines for enabling the simultaneous processing of a plurality of different types of transactions or requests under all conditions. One interface section is organized to include the system visible registers which are accessible for reading and writing by I/O commands received from the system bus. Another section processes memory commands received from the system bus while a further section processes read/write and I/O commands issued to the system bus by the processor.
摘要翻译： 处理器耦合到系统总线，并且包括紧密耦合到本地存储器的高性能微处理器。 处理器在接口级别被组织成多个接口部分，其包括相应数量的状态机，用于在所有条件下能够同时处理多种不同类型的事务或请求。 一个接口部分被组织成包括系统可见寄存器，可通过从系统总线接收的I / O命令进行读写。 另一部分处理从系统总线接收的存储器命令，而另一部分处理由处理器发出到系统总线的读/写和I / O命令。
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公开(公告)号：US5487163A
公开(公告)日：1996-01-23
申请号：US148030
申请日：1993-11-04
申请人： James W. Keeley
发明人： James W. Keeley
IPC分类号： H03K5/135 , H03K5/13 , H03K19/003
CPC分类号： H03K5/135
摘要： A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period. The resulting output signal is directly applied to the input of another synchronously operated bistable device which stores the resulting output signal in response to the next occurring synchronous clock pulse corresponding to a time period which is greater than the time of the metastable time period, minimum delay of the logic part and preset of time of such bistable device.
摘要翻译： 方法和装置通过量化响应于第一同步时钟脉冲接收和存储异步信号的输入时钟双稳态器件的延迟量化同步操作器件的异步信号来提供异步信号的快速同步，使得这种输入时钟双稳态器件具有 亚稳态时间段小于预定的最大延迟周期。 输入时钟双稳态器件的输出信号直接连接到异步操作的逻辑电路部分的输入，该部分被选择以在预定的最小时间周期内提供与对输出信号执行逻辑运算的结果相对应的结果输出信号。 所得到的输出信号被直接施加到另一个同步操作的双稳态器件的输入端，该双稳态器件存储响应于下一个发生的同步时钟脉冲的输出信号，该时钟周期大于亚稳态时间段的时间段，最小延迟 的逻辑部分和这种双稳态设备的时间预设。
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33.发明授权Shared interface apparatus for testing the memory sections of a cache unit 失效用于测试高速缓存单元的存储器部分的共享接口装置
公开(公告)号：US4575792A
公开(公告)日：1986-03-11
申请号：US364051
申请日：1982-03-31
申请人： James W. Keeley
发明人： James W. Keeley
摘要： The circuits of a cache unit constructed from a single board are divided into a cache memory section and a controller section. The cache unit is connectable to the central processing unit (CPU) of a data processing system through the interface circuits of the controller section. Test mode logic circuits included within the cache memory section enable cache memories to be tested without controller interference utilizing the same controller interface circuits.
摘要翻译： 由单板构成的缓存单元的电路被分为高速缓冲存储器部分和控制器部分。 高速缓存单元可通过控制器部分的接口电路连接到数据处理系统的中央处理单元（CPU）。 包括在高速缓冲存储器部分内的测试模式逻辑电路使得能够使用相同的控制器接口电路来测试无需控制器干扰的高速缓存存储器。
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公开(公告)号：US4464717A
公开(公告)日：1984-08-07
申请号：US364052
申请日：1982-03-31
申请人： James W. Keeley , Edwin P. Fisher , John L. Curley
发明人： James W. Keeley , Edwin P. Fisher , John L. Curley
CPC分类号： G11C29/88 , G06F12/126 , G06F2212/1032
摘要： The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.
摘要翻译： 多级组关联高速缓存系统的目录和缓存存储器以存储器位置的级别组织。 循环替换装置用于识别要更换哪一个多级别信息。 该目录包括用于在高速缓冲存储器操作循环期间检测写入目录中的地址中的错误的奇偶校验检测装置。 控制装置将这种奇偶校验错误与指示目录命中的信号组合以产生无效命中检测信号。 响应于第一无效命中检测信号的发生，控制装置对循环装置以及高速缓存系统的其他部分进行调节，以将高速缓存操作限制在那些级别无错误的部分，从而正确地降低缓存操作。
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35.发明授权Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system 有权用于光纤通道仲裁环路系统中多目标桥/路由器的接入公平性的装置和方法公开(公告)号：US08379665B2
公开(公告)日：2013-02-19
申请号：US12475694
申请日：2009-06-01
IPC分类号： H04J3/02
CPC分类号： H04L12/427
摘要： Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.
摘要翻译： 装置和方法通过桥接装置改善了对光纤通道仲裁环（FC-AL）通信介质的公平访问。 增强型桥接器件在当前打开的访问窗口中为通过桥接设备耦合到FC-AL通信介质的所有当前请求设备提供公平的访问。 因此，当在开放访问窗口中存在同时请求时，环路上的所有设备无论是直接耦合还是通过桥接设备都可以确保公平地访问环路。
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36.发明授权Test apparatus for testing a multilevel cache system with graceful degradation capability 失效用于测试具有优雅降级能力的多级缓存系统的测试装置
公开(公告)号：US4686621A
公开(公告)日：1987-08-11
申请号：US510079
申请日：1983-06-30
CPC分类号： G06F12/126 , G06F12/0864 , G11C29/88 , G06F11/2236 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.
摘要翻译： 其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于从目录错误检查电路到被检测为没有错误的那些级别的错误信号选择性地降级缓存操作。 测试装置耦合到控制装置并且操作以响应于从中央处理单元接收到的命令来选择性地改变高速缓存级别的操作状态，用于除了其他高速缓存控制区域之外还能够对这种控制装置进行测试。
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公开(公告)号：US4562536A
公开(公告)日：1985-12-31
申请号：US509825
申请日：1983-06-30
IPC分类号： G06F11/00 , G06F11/10 , G06F11/267 , G06F12/08 , G06F12/12 , G11C29/00 , G11C29/02 , G06F13/00
CPC分类号： G06F11/1666 , G06F11/2215 , G06F12/0864 , G06F12/126 , G11C29/02 , G11C29/88 , G06F11/1064 , G06F11/20 , G06F2201/85 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.
摘要翻译： 一个多级集合关联缓存系统，其目录和高速缓存存储组织到内存级别的位置。 轮询更换装置用于识别要更换哪个级别的信息。 该目录包括用于产生与地址一起写入目录位置的地址校验位的错误检查装置。 响应于来自错误检查装置的错误信号的控制装置将高速缓存操作降级到被检测为没有错误的那些级别。 耦合到替换和检查比特装置的测试错误模式控制装置使得地址校验位响应于从中央处理单元接收到的命令被选择性地强制为不正确的值，从而能够对来自其他的干扰的校验和控制装置进行验证 由中央处理单元发起的操作。
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