公开(公告)号：US11275992B2

公开(公告)日：2022-03-15

申请号：US15983056

申请日：2018-05-17

Applicant: Google LLC

Inventor： Thomas Norrie ,  Olivier Temam ,  Andrew Everett Phelps ,  Norman Paul Jouppi

IPC: G06N3/08 ,  G06N3/063 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.

公开(公告)号：US11182159B2

公开(公告)日：2021-11-23

申请号：US17007569

申请日：2020-08-31

Applicant: Google LLC

Inventor： Thomas Norrie ,  Gurushankar Rajamani ,  Andrew Everett Phelps ,  Matthew Leever Hedlund ,  Norman Paul Jouppi

IPC: G06F9/30 ,  G06N3/04 ,  G06F13/28

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.

公开(公告)号：US20210312011A1

公开(公告)日：2021-10-07

申请号：US17208214

申请日：2021-03-22

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam ,  Jonathan Ross ,  Christopher Aaron Clark

IPC: G06F17/16 ,  G06F7/76 ,  G06F9/30

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

公开(公告)号：US10915318B2

公开(公告)日：2021-02-09

申请号：US16291176

申请日：2019-03-04

Applicant: Google LLC

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/302 ,  G06F9/312 ,  G06F15/76 ,  G06F13/40 ,  G06F13/42 ,  G06F17/16 ,  G06N3/063 ,  G06F9/30 ,  G06F15/80 ,  G06F9/38 ,  G06F7/58 ,  G06F13/36

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US20210026801A1

公开(公告)日：2021-01-28

申请号：US17037286

申请日：2020-09-29

Applicant: Google LLC

Inventor： Kyle Nesbit ,  Andrew Everett Phelps

IPC: G06F15/173 ,  G06F3/06

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

公开(公告)号：US10699188B2

公开(公告)日：2020-06-30

申请号：US15686615

申请日：2017-08-25

Applicant: Google LLC

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06F15/80 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US10592583B2

公开(公告)日：2020-03-17

申请号：US16283913

申请日：2019-02-25

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam ,  Jonathan Ross ,  Christopher Aaron Clark

IPC: G06F7/16 ,  G06F17/16 ,  G06F7/76 ,  G06F9/30 ,  G06N3/063 ,  G06N3/08

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

公开(公告)号：US10514891B1

公开(公告)日：2019-12-24

申请号：US16435075

申请日：2019-06-07

Applicant: Google LLC

Inventor： Hsin-Jung Yang ,  Andrew Everett Phelps

IPC: G06F7/485 ,  G06F7/499 ,  G06F9/30

Abstract: Methods, systems, and apparatus, including an apparatus for adding three or more floating-point numbers. In one aspect, a method includes receiving, for each of three or more operands, a set of bits that include a floating-point representation of the operand. A given operand is identified. For each other operand, the mantissa bits of the operand are shifted such that the bits of the operand align with the bits of the given operand. A sticky bit for each other operand is determined. An overall sticky bit value is determined based on each sticky bit. The overall sticky bit value is zero whenever all of the sticky bits are zero or at least two sticky bits are non-zero and do not match. The overall sticky bit value matches the value of each non-zero sticky bit whenever all of the non-zero sticky bits match or there is only one non-zero sticky bit.

公开(公告)号：US20190354570A1

公开(公告)日：2019-11-21

申请号：US16528826

申请日：2019-08-01

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam ,  Jonathan Ross ,  Christopher Aaron Clark

IPC: G06F17/16 ,  G06F9/30 ,  G06F7/76

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

公开(公告)号：US10261786B2

公开(公告)日：2019-04-16

申请号：US15454214

申请日：2017-03-09

Applicant: Google LLC

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/302 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06N3/063 ,  G06F9/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.