公开(公告)号：US20180012095A1

公开(公告)日：2018-01-11

申请号：US15695681

申请日：2017-09-05

Applicant: HUAWEI TECHNOLOGIES CO.,LTD. ,  NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： Hao Yu ,  Yuhao Wang ,  Leibin Ni ,  Wei Yang ,  Junfeng Zhao ,  Shihai Xiao

IPC: G06K9/00 ,  G06K9/62

CPC classification number: G06K9/00973 ,  G06K9/00 ,  G06K9/6201

Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

公开(公告)号：US20170263295A1

公开(公告)日：2017-09-14

申请号：US15607360

申请日：2017-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Wei Yang ,  Junfeng Zhao

IPC: G11C8/16 ,  G06F3/06

CPC classification number: G11C8/16 ,  G06F3/0659 ,  G11C8/10

Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.