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公开(公告)号：US11681452B2
公开(公告)日：2023-06-20
申请号：US17569911
申请日：2022-01-06
发明人： Shihai Xiao , Florian Longnos , Wei Yang
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/0679 , G06F12/0646 , G06F13/1673 , G06F3/067
摘要： A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.
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公开(公告)号：US20210335417A1
公开(公告)日：2021-10-28
申请号：US17370755
申请日：2021-07-08
发明人： Xing Hu , Chuanzeng Liang , Shihai Xiao , Kanwen Wang
IPC分类号： G11C11/406
摘要： A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.
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公开(公告)号：US20200066330A1
公开(公告)日：2020-02-27
申请号：US16599980
申请日：2019-10-11
发明人： Xing Hu , Chuanzeng Liang , Shihai Xiao , Kanwen Wang
IPC分类号： G11C11/406
摘要： A memory refresh method is applied to a computer system including a memory controller and a dynamic random access memory (DRAM). The memory controller receives access requests including access requests for accessing a first rank of multiple ranks in the DRAM. When a quantity of the access requests for accessing the first rank is greater than 0 and less than a second threshold, the memory controller refreshes the first rank. The first rank may be refreshed in time even if the first rank cannot be in an idle state.
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公开(公告)号：US11705180B2
公开(公告)日：2023-07-18
申请号：US17370755
申请日：2021-07-08
发明人： Xing Hu , Chuanzeng Liang , Shihai Xiao , Kanwen Wang
IPC分类号： G11C11/406
CPC分类号： G11C11/40618
摘要： A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.
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公开(公告)号：US11289159B2
公开(公告)日：2022-03-29
申请号：US16720406
申请日：2019-12-19
发明人： Florian Longnos , Engin Ipek , Shihai Xiao
摘要： A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.
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公开(公告)号：US11074958B2
公开(公告)日：2021-07-27
申请号：US16600034
申请日：2019-10-11
发明人： Xing Hu , Chuanzeng Liang , Shihai Xiao , Kanwen Wang
IPC分类号： G11C16/04 , G11C11/406
摘要： A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.
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公开(公告)号：US20180321942A1
公开(公告)日：2018-11-08
申请号：US16037767
申请日：2018-07-17
发明人： Hao Yu , Yuhao Wang , Junfeng Zhao , Wei Yang , Shihai Xiao , Leibin Ni
CPC分类号： G06F9/30036 , G06F7/00 , G06F9/3001 , G06F9/30025 , G06F13/00 , G06F17/16 , G06J1/00 , G06N3/0635 , G11C5/02 , G11C7/1006 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2213/71 , G11C2213/77
摘要： Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.
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公开(公告)号：US20240273164A1
公开(公告)日：2024-08-15
申请号：US18641086
申请日：2024-04-19
发明人： Guohao Dai , Zhenhua Zhu , Yu Wang , Shihai Xiao , Tianyu Fu , Xuecang Zhang
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： This application discloses a data processing apparatus controlling method and apparatus, to reduce processing time. The method includes: obtaining two target data groups, where the two target data groups are 1st data groups in two data sets, there are a plurality of first data groups in a first data set, key values of any data group in the data set are less than key values in a data group following the any data group; and when a largest key value in a first target data group is less than or equal to a largest key value in a second target data group, using a next first data group of the first target data group as another first target data group. Therefore, an operation amount can be reduced, and operation efficiency can be improved.
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公开(公告)号：US11231864B2
公开(公告)日：2022-01-25
申请号：US16927066
申请日：2020-07-13
发明人： Shihai Xiao , Florian Longnos , Wei Yang
摘要： A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.
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公开(公告)号：US10976800B2
公开(公告)日：2021-04-13
申请号：US15882612
申请日：2018-01-29
发明人： RenHua Yang , Junfeng Zhao , Wei Yang , Shihai Xiao , Yinyin Lin , Yi Wei
IPC分类号： G06F1/3287 , G06F3/06 , G06F1/3228 , G06F1/3234 , G06F9/4401 , G06F12/0868
摘要： An electronic device includes a processor, a volatile memory, and a non-volatile memory. The non-volatile memory stores a first operating system, and the electronic device works in a first working mode and a second working mode. When the electronic device is in the first working mode, a second operating system is run in the volatile memory. When the processor detects that the electronic device reaches a preset condition for entering the second working mode, the non-volatile memory is enabled, and non-system data in the volatile memory is moved to the non-volatile memory. The non-system data does not include the second operating system. After the movement of the non-system data is completed, the volatile memory is disabled, and the first operating system is run in the non-volatile memory, so that the electronic device enters the second working mode.
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