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126 条记录 (耗时 0.044 秒)

    Unified Collector Structure for Multi-Bank Register File
    31.
    发明申请
    Unified Collector Structure for Multi-Bank Register File 有权
    多银行登记册统一采集器结构

    公开(公告)号：US20110072243A1

    公开(公告)日：2011-03-24

    申请号：US12875843

    申请日：2010-09-03

    申请人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

    发明人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3012 ,  G06F9/30098 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

    摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

    摘要翻译： 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

    Processing an indirect branch instruction in a SIMD architecture
    32.
    发明授权
    Processing an indirect branch instruction in a SIMD architecture 有权
    在SIMD架构中处理间接分支指令

    公开(公告)号：US07761697B1

    公开(公告)日：2010-07-20

    申请号：US11557082

    申请日：2006-11-06

    申请人： Brett W. Coon ,  John Erik Lindholm ,  Peter C. Mills ,  John R. Nickolls

    发明人： Brett W. Coon ,  John Erik Lindholm ,  Peter C. Mills ,  John R. Nickolls

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/30072 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/322 ,  G06F9/3851 ,  G06F9/3887

    摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is an indirect branch instruction, and processing the indirect branch instruction as a sequence of two-way branches to execute an indirect branch instruction with multiple branch addresses. Indirect branch instructions may be used to allow greater flexibility since the branch address or multiple branch addresses do not need to be determined at compile time.

    摘要翻译： 被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。 多线程处理单元被配置为执行以下步骤：获取程序指令，确定程序指令是间接分支指令，以及将间接分支指令处理为双向分支序列，以执行具有多个分支的间接分支指令 地址 可以使用间接分支指令来允许更大的灵活性，因为在编译时不需要确定分支地址或多个分支地址。

    ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR
    33.
    发明申请
    ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR 审中-公开
    多功能微处理器中的交叉螺纹指令分配

    公开(公告)号：US20100122067A1

    公开(公告)日：2010-05-13

    申请号：US12690225

    申请日：2010-01-20

    申请人： John Erik Lindholm ,  Brett Coon ,  Simon S. Moy

    发明人： John Erik Lindholm ,  Brett Coon ,  Simon S. Moy

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.

    摘要翻译： 诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。 提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。 调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。 如果有多个功能单元可用，则可以并行调度多个指令。

    Structured programming control flow using a disable mask in a SIMD architecture
    34.
    发明授权
    Structured programming control flow using a disable mask in a SIMD architecture 有权
    在SIMD架构中使用禁用掩码的结构化编程控制流程

    公开(公告)号：US07617384B1

    公开(公告)日：2009-11-10

    申请号：US11669513

    申请日：2007-01-31

    申请人： Brett W. Coon ,  John Erik Lindholm ,  Svetoslav D. Tzvetkov

    发明人： Brett W. Coon ,  John Erik Lindholm ,  Svetoslav D. Tzvetkov

    IPC分类号： G06F15/80

    CPC分类号： G06F9/3851 ,  G06F9/30072 ,  G06F9/3885 ,  G06F9/3887

    摘要： One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. Threads that exit a program are identified as idle by a disable mask. Other threads that are disabled may be enabled once the divergent threads reach an instruction that enables the disabled threads. Use of the disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture.

    摘要翻译： 被配置为管理SIMD线程组中的发散线程的计算系统的一个实施例包括被配置为存储用于处理控制指令的状态信息的堆栈。 并行处理单元被配置为执行在执行条件控制指令期间确定一个或多个线程是否发散的步骤。 退出程序的线程被禁用掩码标识为空闲。 禁用的其他线程可以在分支线程达到启用禁用线程的指令后启用。 禁用掩码的使用允许在多线程SIMD架构中使用条件返回和中断指令。

    Method, apparatus and article of manufacture for a vertex attribute buffer in a graphics processor
    39.
    发明授权
    Method, apparatus and article of manufacture for a vertex attribute buffer in a graphics processor 有权
    用于图形处理器中的顶点属性缓冲器的方法，装置和制造

    公开(公告)号：US06515671B1

    公开(公告)日：2003-02-04

    申请号：US09454525

    申请日：1999-12-06

    申请人： John Erik Lindholm ,  Simon Moy

    发明人： John Erik Lindholm ,  Simon Moy

    IPC分类号： G06T120

    CPC分类号： G06T1/60 ,  G06T15/005

    摘要： A method, apparatus and article of manufacture are provided for managing vertex data in a vertex buffer. First, vertex data is received and stored in the vertex buffer. Thereafter, the vertex data is outputted from the vertex buffer to a processing module. During operation, a plurality of command bits is passed from the vertex buffer for determining a manner in which the vertex data is inputted and processed in the input buffer of the processing module. Such command bits are received from a command bit source. Further, a plurality of mode bits indicative of a status of a plurality of modes of process operations is passed. Such mode bits are received from a mode bit source. The mode bits are adapted for determining a manner in which the vertex data is processed in the processing module.

    摘要翻译： 提供了一种用于管理顶点缓冲器中的顶点数据的方法，装置和制品。 首先，顶点数据被接收并存储在顶点缓冲器中。 此后，顶点数据从顶点缓冲器输出到处理模块。 在操作期间，从顶点缓冲器传送多个命令位，以确定在处理模块的输入缓冲器中输入和处理顶点数据的方式。 这样的命令位从命令位源接收。 此外，通过表示多种处理操作模式的状态的多个模式比特。 从模式位源接收这样的模式位。 模式位适于确定在处理模块中处理顶点数据的方式。