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公开(公告)号：US06833831B2
公开(公告)日：2004-12-21
申请号：US10083623
申请日：2002-02-26
IPC分类号： G06T120
CPC分类号： G06F9/30079 , G06F9/3879 , G06T1/20
摘要： A method and system for synchronizing data streams and transferring control of resources between two processes in a graphics processor is described. The method allows for completion of pending operations of a first process in a manner that ensures the first process may be restarted without loss of data or process sequence. The processing pipeline is allowed to complete normal execution of all process operations required to reach a first process step that may be interrupted. The second process is initiated when the interruption of the first process is verified. Upon completion of the second process, the first process is reactivated at the next process step in sequence.
摘要翻译： 描述了用于在图形处理器中的两个进程之间同步数据流和传送资源控制的方法和系统。 该方法允许以确保可以重新启动第一进程而不丢失数据或处理序列的方式完成第一进程的挂起操作。 允许处理流水线完成所有处理操作的正常执行，以达到可能被中断的第一流程步骤。 当验证第一过程的中断时，启动第二过程。 在第二过程完成时，第一过程在下一个处理步骤中依次重新激活。
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公开(公告)号：US06597363B1
公开(公告)日：2003-07-22
申请号：US09378637
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
IPC分类号： G06T120
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.
摘要翻译： 描述了包括许多子结构的图形处理器和方法，包括专用子系统，子处理器，设备，架构和相应的过程。 本发明的实施例可以包括延迟着色，出血帧缓冲器和多级隐藏表面去除处理以及其他结构和/或程序中的一个或多个。 本发明的实施例被设计为提供具有Phong着色，子像素抗锯齿，纹理和凹凸映射的高性能3D图形。
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公开(公告)号：US06456737B1
公开(公告)日：2002-09-24
申请号：US09641610
申请日：2000-08-17
IPC分类号： G06T120
CPC分类号： G06T7/0075 , G01C11/06 , G06K9/32 , G06K9/6211 , G06T1/20 , G06T7/593 , G06T2207/10012 , H04N13/111 , H04N13/167 , H04N13/189 , H04N13/194 , H04N13/239 , H04N13/246 , H04N13/296 , H04N2013/0081
摘要： A powerful, scaleable, and reconfigurable image processing system and method of processing data therein is described. This general purpose, reconfigurable engine with toroidal topology, distributed memory, and wide bandwidth I/O are capable of solving real applications at real-time speeds. The reconfigurable image processing system can be optimized to efficiently perform specialized computations, such as real-time video and audio processing. This reconfigurable image processing system provides high performance via high computational density, high memory bandwidth, and high I/O bandwidth. Generally, the reconfigurable image processing system and its control structure include a homogeneous array of 16 field programmable gate arrays (FPGA) and 16 static random access memories (SRAM) arranged in a partial torus configuration. The reconfigurable image processing system also includes a PCI bus interface chip, a clock control chip, and a datapath chip. It can be implemented in a single board. It receives data from its external environment, computes correspondence, and uses the results of the correspondence computations for various post-processing industrial applications. The reconfigurable image processing system determines correspondence by using non-parametric local transforms followed by correlation. These non-parametric local transforms include the census and rank transforms. Other embodiments involve a combination of correspondence, rectification, a left-right consistency check, and the application of an interest operator.
摘要翻译： 描述了一种强大的，可扩展的和可重新配置的图像处理系统及其中的数据处理方法。 这种具有环形拓扑，分布式存储器和宽带宽I / O的通用可重构引擎能够以实时速度解决实际应用。 可重构图像处理系统可以被优化以有效地执行诸如实时视频和音频处理的专门计算。 该可重构图像处理系统通过高计算密度，高存储带宽和高I / O带宽提供高性能。 通常，可重构图像处理系统及其控制结构包括以局部环形配置布置的16个现场可编程门阵列（FPGA）和16个静态随机存取存储器（SRAM）的均匀阵列。 可重构图像处理系统还包括PCI总线接口芯片，时钟控制芯片和数据通路芯片。 它可以在单板中实现。 它从其外部环境接收数据，计算对应关系，并使用各种后处理工业应用程序的对应计算结果。 可重构图像处理系统通过使用非参数局部变换随后进行相关来确定对应关系。 这些非参数局部变换包括人口普查和秩变换。 其他实施例涉及对应，整改，左右一致性检查和感兴趣操作者的应用的组合。
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公开(公告)号：US06377271B1
公开(公告)日：2002-04-23
申请号：US09293643
申请日：1999-04-17
申请人： Hidemasa Muta , Tatsuya Sobue , Aya Mori
发明人： Hidemasa Muta , Tatsuya Sobue , Aya Mori
IPC分类号： G06T120
CPC分类号： H04N19/186 , H04N19/507
摘要： The image data transferring apparatus of this invention determines that the change in the image is very small when a change in the image is not detected during a given time period, for example, and generates transmission data which causes image data displaying a full color image of, for example, 24 bits per pixel to be displayed in the receiving side in a relatively small number of frames in a unit time for transmission. Conversely, the image data transferring apparatus transmits reduced color data which is reduced from 24 bits per pixel to 4 bits per pixel in a relatively large number of frames in a unit time to the receiving side when it is determined that many changes are included in the image.
摘要翻译： 本发明的图像数据传送装置例如在给定时间段内，当检测到图像的变化时，确定图像的变化非常小，并且生成使图像数据显示全色图像的发送数据 例如，在单位时间内以相对较少数量的帧显示在接收侧的每像素24位。 相反地，图像数据传送装置将缩小的彩色数据从单位时间内的相对大数量的帧中的每像素的24比特减少到接收侧，当确定许多改变被包括在 图片。
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公开(公告)号：US06369823B2
公开(公告)日：2002-04-09
申请号：US09778159
申请日：2001-02-05
申请人： Akio Ohba
发明人： Akio Ohba
IPC分类号： G06T120
摘要： A main CPU 11, a main memory 12, a main DMAC (direct memory access controller) 13 and a picture processing unit (graphic processing unit or GPU) 15 are interconnected over a main bus 1. In an input/output unit of each of the main CPU 11 and the GPU 15 are mounted programmable packet engines (PPE) 112, 152 capable of modifying the data packetizing/unpacketizing sequence in order to perform packet transfer with freedom in the packet form. This affords freedom to the packet form to realize efficient development and packing of packet data and efficient drawing processing.
摘要翻译： 主CPU 11，主存储器12，主DMAC（直接存储器存取控制器）13和图像处理单元（图形处理单元或GPU）15通过主总线1互连。在每个的输入/输出单元 主CPU 11和GPU 15安装有能够修改数据分组/解包序列的可编程分组引擎（PPE）112,152，以便以分组形式自由地执行分组传送。 这为数据包形式提供了自由，实现了分组数据的高效开发和打包以及高效的绘图处理。
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公开(公告)号：US06289115B1
公开(公告)日：2001-09-11
申请号：US09249093
申请日：1999-02-12
申请人： Hideya Takeo
发明人： Hideya Takeo
IPC分类号： G06T120
CPC分类号： G06T1/00 , G06F19/00 , G06F19/321 , Y10S128/92 , Y10S128/922
摘要： A medical network system comprising a multitude of reference terminals for referring to diagnosis images can be constructed at low cost and the reference terminals can carry out fast display equivalent to that by a high performance workstation for diagnosis. An image server is loaded with a web server, separately from a server (DICOM server) for providing image data based on a protocol specific to a medical system, so that a web connection to the image server becomes possible. An image processing server loaded with an image processing component for carrying out image processing for display is provided, separately from the image server. The reference terminals obtain image data and a display program from the image server via the web connection, cause the image processing server to execute image processing on the obtained image data, and carry out display alone of the processed image.
摘要翻译： 可以以低成本构建包括用于参考诊断图像的多个参考终端的医疗网络系统，并且参考终端可以执行与用于诊断的高性能工作站相当的快速显示。 图像服务器被加载有与服务器（DICOM服务器）分离的web服务器，用于基于特定于医疗系统的协议提供图像数据，使得到图像服务器的web连接成为可能。 与图像服务器分离地提供装载有用于执行用于显示的图像处理的图像处理部件的图像处理服务器。 基准端子通过网络连接从图像服务器获取图像数据和显示程序，使得图像处理服务器对获得的图像数据执行图像处理，并且仅对处理的图像进行显示。
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公开(公告)号：US06195105B1
公开(公告)日：2001-02-27
申请号：US09088190
申请日：1998-06-01
IPC分类号： G06T120
CPC分类号： G06F9/3877 , G06F9/30025
摘要： A method and apparatus for improved concurrency within a video graphics process by generating culling information from geometry information. The geometry information corresponds to an image to be rendered, and the culling information indicates the triangles of the objects of the image that are in a front-facing or back-facing position. Having generated the culling information, set-up information is generated therefrom. The set-up information provides rendering data for the triangles of the object of the image being rendered. Next, pixel data is generated for a triangle based on the set-up information. To improve the concurrency, the queuing and the retrieval of the culling information and the set-up information from non-local memory are controlled such that the generating of the culling information, the set-up information, and the pixel data is done with improved concurrency.
摘要翻译： 一种用于通过从几何信息生成剔除信息来改善视频图形过程中的并发性的方法和装置。 几何信息对应于要呈现的图像，并且剔除信息指示图像的处于前向或后向位置的图像的三角形。 生成了拣选信息后，从其生成设置信息。 设置信息提供正在呈现的图像的对象的三角形的渲染数据。 接下来，基于设置信息为三角形生成像素数据。 为了提高并发性，对来自非本地存储器的排队信息和设置信息的排队和检索进行控制，使得剔除信息，建立信息和像素数据的生成被改进 并发性
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公开(公告)号：US06809735B1
公开(公告)日：2004-10-26
申请号：US10042882
申请日：2002-01-08
申请人： John Stauffer , Bob Beretta , Ken Dyke
发明人： John Stauffer , Bob Beretta , Ken Dyke
IPC分类号： G06T120
CPC分类号： G06F9/5016 , G06F12/10 , G09G5/363 , G09G5/399
摘要： Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.
摘要翻译： 图形资源通过图形硬件和图形客户端之间的接口进行虚拟化。 该界面在多个图形客户端分配图形资源，处理从图形客户端访问图形资源的命令，并解决了客户端之间图形资源的冲突。
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9.发明授权公开(公告)号：US06806880B1
公开(公告)日：2004-10-19
申请号：US09688978
申请日：2000-10-17
申请人： Shrijeet Mukherjee , David M. Blythe , David G. Yu
发明人： Shrijeet Mukherjee , David M. Blythe , David G. Yu
IPC分类号： G06T120
CPC分类号： G06T1/20
摘要： A system and method for controlling graphics rendering pipelines. The pipeline is unstalled in response to a display interval complete signal which allows pipeline processing to proceed even at the beginning of a tolerance interval. A stall controller unstalls processing of the graphics data in the graphics rendering pipeline when a display interval complete signal has been generated. A stall token installer inserts stall tokens in between frames of the graphics data. A queue stores frame complete markers in an order matching the order of stall tokens inserted in between frames of graphics data.
摘要翻译： 一种用于控制图形渲染管线的系统和方法。 响应于允许流水线处理甚至在公差间隔开始时进行的显示间隔完成信号，管道被解除安装。 当生成显示间隔完成信号时，失速控制器对图形渲染管线中的图形数据进行处理。 停顿令牌安装程序在图形数据的帧之间插入停顿令牌。 队列以与插入在图形数据帧之间的停顿令牌的顺序相匹配的顺序存储帧完整标记。
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公开(公告)号：US06791552B2
公开(公告)日：2004-09-14
申请号：US09362534
申请日：1999-07-28
IPC分类号： G06T120
CPC分类号： G06T15/005
摘要： Digital video processing apparatus comprising: a plurality of render processors arranged in an operational sequence, each operable to render an output result relating to an image of a video signal from input data relating to that and/or other images received from a preceding render processor in the operational sequence; and a render controller for controlling rendering operation of the render processors; each render processor being operable to communicate dependency data to the render controller, indicating which images must be rendered by a preceding render processor in order for that render processor to render output data relating to a required image; and the render controller being operable to control operation of the render processors so that images required by each render processor are rendered by preceding render processors in the operational sequence.
摘要翻译： 数字视频处理装置，包括：以操作顺序排列的多个渲染处理器，每个渲染处理器可操作以从与从前一渲染处理器接收的和/或其他图像有关的输入数据呈现与视频信号的图像有关的输出结果 操作顺序; 以及用于控制渲染处理器的渲染操作的渲染控制器; 每个渲染处理器可操作以将依赖性数据传送到渲染控制器，指示由先前的渲染处理器必须呈现哪些图像，以使该渲染处理器呈现与所需图像相关的输出数据; 并且渲染控制器可操作以控制渲染处理器的操作，使得每个渲染处理器所需的图像在操作顺序中由前面的渲染处理器渲染。
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