公开(公告)号：US07966446B2

公开(公告)日：2011-06-21

申请号：US11451802

申请日：2006-06-13

申请人： Joo-Sun Choi

发明人： Joo-Sun Choi

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0802

摘要： A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.

摘要翻译： 存储器系统包括用于产生控制信号的控制器和用于从控制器接收控制信号的主存储器。 次存储器耦合到主存储器，辅存储器适于从主存储器接收控制信号。 控制信号定义要由主存储器和次存储器之一执行的背景操作以及由另一个主存储器和次存储器执行的前景操作。 主存储器和辅助存储器通过点对点链路连接。 主存储器和次存储器之间的至少一个链路可以是至少部分序列化的链路。 主存储器和次存储器中的至少一个可以包括机载内部高速缓冲存储器。

公开(公告)号：US07778042B2

公开(公告)日：2010-08-17

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K1/11

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07692945B2

公开(公告)日：2010-04-06

申请号：US11484173

申请日：2006-07-11

申请人： Joo-Sun Choi

发明人： Joo-Sun Choi

IPC分类号： G11C5/06

CPC分类号： G11C5/04 ,  G11C7/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected together, typically by point-to-point links. When the memory system configuration is such that at least one of the ports in at least one of the memory devices is not used, one or more other ports can use the pins that may otherwise have been used by the unused ports. As a result, a set of reconfigurable, shared pins is defined in which two ports share the pins. The port that is not being used in a particular application for the memory device is not connected to the shared pins, and another port that is being used in the application is connected to the shared pins. This allows for the used of fewer package pins and, consequently, reduced package size.

摘要翻译： 存储器系统和存储器模块包括多个存储器件，每个存储器件具有多个，例如， 四个用于发送和接收命令信号的端口，写数据信号和读数据信号。 其中一个存储设备连接到主机或控制器，其余存储器通常通过点对点链路连接在一起。 当存储器系统配置使得至少一个存储器设备中的至少一个端口不被使用时，一个或多个其他端口可以使用另外可能由未使用的端口使用的引脚。 因此，定义了一组可重新配置的共享引脚，其中两个端口共享引脚。 在存储器件的特定应用中未使用的端口未连接到共享引脚，并且应用中正在使用的另一个端口连接到共享引脚。 这允许使用更少的封装引脚，从而减少封装尺寸。

公开(公告)号：US20080247212A1

公开(公告)日：2008-10-09

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07405949B2

公开(公告)日：2008-07-29

申请号：US11603648

申请日：2006-11-22

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K7/14

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。