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    Non-volatile memory (NVM) based method for performance acceleration of containers
    31.
    发明授权
    Non-volatile memory (NVM) based method for performance acceleration of containers 有权

    公开(公告)号：US11449355B2

    公开(公告)日：2022-09-20

    申请号：US16773004

    申请日：2020-01-27

    Applicant: Huazhong University of Science and Technology

    Inventor： Hai Jin ,  Song Wu ,  Qizhi Tang

    IPC: G06F9/455 ,  G06F8/60 ,  G06K9/62

    Abstract: The present disclosure discloses a NVM-based method for performance acceleration of containers. The method comprises classifying each image layer of mirror images as either an LAL (Layer above LDL) or an LBL (Layer below LDL) during deployment of containers; storing the LALs into a non-volatile memory and selectively storing each said LBL into one of the non-volatile memory and a hard drive; acquiring hot image files required by the containers during startup and/or operation of the containers and storing the hot image files required by the containers into the non-volatile memory; and sorting the mirror images in terms of access frequency according to at least numbers of times of access to the hot image files so as to release the non-volatile memory currently occupied by the mirror image having the lowest access frequency when the non-volatile memory is short of storage space.

    FPGA coprocessor with sparsity and density modules for execution of low and high parallelism portions of graph traversals
    35.
    发明授权
    FPGA coprocessor with sparsity and density modules for execution of low and high parallelism portions of graph traversals 有权

    公开(公告)号：US11263168B2

    公开(公告)日：2022-03-01

    申请号：US16722082

    申请日：2019-12-20

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiaofei Liao ,  Hai Jin ,  Long Zheng ,  Chengbo Yang

    IPC: G06F9/38 ,  G06F15/82 ,  G06F15/78 ,  G06F15/76 ,  G06F16/901

    Abstract: An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.

    Hardware-supported 3D-stacked NVM data compression method and system thereof
    38.
    发明授权
    Hardware-supported 3D-stacked NVM data compression method and system thereof 有权

    公开(公告)号：US10996856B2

    公开(公告)日：2021-05-04

    申请号：US16750655

    申请日：2020-01-23

    Applicant: Huazhong University of Science and Technology

    Inventor： Haikun Liu ,  Xiaofei Liao ,  Hai Jin ,  Yuanyuan Ye

    IPC: G03F3/06 ,  G06F3/06 ,  G11C7/10 ,  H01L25/065

    Abstract: The present disclosure involves a hardware-supported 3D-stacked NVM data compression method and system, involving setting a first identifier to mark a compression state of written-back data, the method at least comprising steps of: dividing the written-back data into a plurality of sub-blocks and acquiring a plurality of first output results through OR operations among the sub-blocks, respectively, or acquiring a plurality of second output results through exclusive OR operations among the sub-blocks, and determining a compression strategy for the written-back data based on the first output results or the second output results; and setting a second identifier to mark a storing means of the written-back data so that the second identifier is in pair with the first identifier, and configuring a storage strategy for the written-back data that includes at least rotating the second identifier.

    Method of memory estimation and configuration optimization for distributed data processing system
    39.
    发明授权
    Method of memory estimation and configuration optimization for distributed data processing system 有权

    公开(公告)号：US10725754B2

    公开(公告)日：2020-07-28

    申请号：US16216155

    申请日：2018-12-11

    Applicant: Huazhong University of Science and Technology

    Inventor： Xuanhua Shi ,  Hai Jin ,  Zhixiang Ke ,  Wenchao Wu

    IPC: G06F9/44 ,  G06F8/41 ,  G06F11/34 ,  G06F11/36

    Abstract: The present invention relates to a method of memory estimation and configuration optimization for a distributed data processing system involves performing match between an application data stream and a data feature library, wherein the application data stream has received analysis and processing on conditional branches and/or loop bodies of an application code in a Java archive of the application, estimating a memory limit for at least one stage of the application based on the successful matching result, optimizing configuration parameters of the application accordingly, and acquiring static features and/or dynamic features of the application data based on running of the optimized application and performing persistent recording. Opposite to machine-learning-based memory estimation that does not ensure accuracy and fails to provide fine-grained estimation for individual stages, this method uses application analysis and existing data feature to estimate overall memory occupation more precisely and to estimate memory use of individual job stages for more fine-grained configuration optimization.

    Method and system for CSI-based fine-grained gesture recognition
    40.
    发明授权
    Method and system for CSI-based fine-grained gesture recognition 有权

    公开(公告)号：US10592736B2

    公开(公告)日：2020-03-17

    申请号：US16105005

    申请日：2018-08-20

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Jiang Xiao ,  Yuxi Wang ,  Hai Jin ,  Mingxuan Ni

    IPC: G06K9/00 ,  G06K9/03 ,  G06F40/232 ,  G06F40/20

    Abstract: The invention provides a method for CSI-based fine-grained gesture recognition, wherein the method comprises the following steps: determining a start point, an end point, a velocity, a direction and/or an inflection point of at least one stroke gesture in multiple dimensions according to an eigenvalue of channel state information; dividing the strokes according to the start point, the end point, the velocity, the direction and/or the inflection point of the stroke using a machine learning method and forming a stroke sequence; building a stroke decipherment model according to frequencies of the strokes appearing in natural language rules and/or scientific language rules and/or connection rules between the strokes; and dividing and recognizing the stroke sequence as a letter sequence, a radical sequence, a numeral sequence and/or a pattern sequence conforming to the natural language rules and/or the scientific language rules using the stroke decipherment model. The present invention involves recognizing strokes of characters from finger gesture, and then recovering characters from the strokes, so as to enrich types of languages that can be recognized from finger gesture and enhance recognition accuracy of gesture writing.

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