公开(公告)号：US20070030042A1

公开(公告)日：2007-02-08

申请号：US11412803

申请日：2006-04-28

Applicant: Jun-Bae Kim ,  Hyun-Ju Lee

Inventor： Jun-Bae Kim ,  Hyun-Ju Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/089

Abstract: A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

Abstract translation: 用于产生锁定到外部时钟信号的内部时钟信号的延迟锁定环路包括：用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测器; 延迟单元控制器，用于响应于相位检测器的输出信号产生控制信号和选择信号; 可变延迟装置（VDD），响应于控制信号和选择信号，在VDD输出线上产生外部时钟信号的延迟版本，该可变延迟装置被配置为使得如果外部时钟信号经历 从第一频率改变到与第一频率显着不同的第二频率，则VDD输出线上的合成负载仍然保持基本相同。

公开(公告)号：US20050088564A1

公开(公告)日：2005-04-28

申请号：US10763984

申请日：2004-01-23

Applicant: Sang-Ho Kim ,  Yeong-Seop Lee ,  Do-Hyung Lee ,  Hyun-Ju Lee

Inventor： Sang-Ho Kim ,  Yeong-Seop Lee ,  Do-Hyung Lee ,  Hyun-Ju Lee

IPC: H01L27/14 ,  G02B7/02 ,  H01L23/00 ,  H01L27/146 ,  H04N5/225 ,  H04N5/247 ,  H04N5/335

CPC classification number: H04N5/2253

Abstract: Disclosed are an image sensor module of a camera and an assembling method thereof capable of simultaneously bonding a circuit pattern and an infrared ray filter to an upper surface of a circuit board section. The image sensor module has the circuit board section including a bonding part made of transparent material. The circuit board section has an upper surface onto which the circuit pattern and the infrared ray filter are simultaneously bonded. An image sensor chip is bonded to a lower surface of the circuit board section using a flip chip bonding technique. A lens holder is bonded to the upper surface of the circuit board section using an epoxy bonding process. A lens assembly is bonded to an upper surface of the lens holder using the epoxy bonding process.

Abstract translation: 公开了一种摄像机的图像传感器模块及其组合方法，其能够将电路图案和红外线滤波器同时地接合到电路板部分的上表面。 图像传感器模块具有包括由透明材料制成的接合部分的电路板部分。 电路板部分具有同时结合电路图案和红外线滤光器的上表面。 使用倒装芯片接合技术将图像传感器芯片接合到电路板部分的下表面。 使用环氧树脂粘合工艺将透镜保持器结合到电路板部分的上表面。 使用环氧树脂粘合工艺将透镜组件粘合到透镜保持器的上表面。

公开(公告)号：US06509263B1

公开(公告)日：2003-01-21

申请号：US09710953

申请日：2000-11-14

Applicant: Young-Hoon Park ,  Hyun-Ju Lee ,  Eun-Young Minn

Inventor： Young-Hoon Park ,  Hyun-Ju Lee ,  Eun-Young Minn

IPC: H01L218242

CPC classification number: H01L27/10855 ,  H01L21/76886 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891

Abstract: A method for fabricating a semiconductor device to reduce the contact resistance by enhancing the surface concentration of doped polysilicon in a semiconductor substrate divided into active and field regions, comprises the steps of forming a plurality of word lines each having a cap insulating layer with a predetermined interval between adjacent word lines on the substrate, forming source/drain impurity regions in the active regions adjacent to both sides of each of the word lines, forming insulating sidewalls on both sides of each of the word lines, forming capacitor node plugs and bit line contact plugs on the source/drain impurity regions, forming a plurality of bit lines in the direction perpendicular to the word lines with a predetermined interval between adjacent bit lines by forming bit line contact holes contacting the bit line contact plugs in a first insulating interlayer deposited on the substrate, forming storage electrode contact holes to expose the capacitor node plugs in a second insulating interlayer deposited over the substrate, and subjecting the storage electrode contact holes to heat treatment before implanting impurity ions through the storage electrode contact holes into the active regions to grow the storage electrodes.

Abstract translation: 一种半导体器件的制造方法，其特征在于，形成多个字线，所述半导体器件通过提高被划分为有源场和区域的半导体衬底中的掺杂多晶硅的表面浓度来降低接触电阻， 在衬底上的相邻字线之间的间隔，在与每个字线的两侧相邻的有源区域中形成源极/漏极杂质区域，在每个字线的两侧形成绝缘侧壁，形成电容器节点插塞和位线 接触插塞在源极/漏极杂质区上，通过在第一绝缘夹层中形成与位线接触插塞接触的位线接触孔，在相邻位线之间以预定间隔在垂直于字线的方向上形成多个位线 在基板上形成存储电极接触孔，露出电容器节点插入 沉积在衬底上的第二绝缘层，以及在将杂质离子通过存储电极接触孔注入有源区域之前对存储电极接触孔进行热处理，以使存储电极生长。