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12 条记录 (耗时 0.023 秒)

    Delay locked loop
    1.
    发明申请
    Delay locked loop 有权
    延迟锁定环路

    公开(公告)号：US20070030042A1

    公开(公告)日：2007-02-08

    申请号：US11412803

    申请日：2006-04-28

    申请人： Jun-Bae Kim ,  Hyun-Ju Lee

    发明人： Jun-Bae Kim ,  Hyun-Ju Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

    摘要翻译： 用于产生锁定到外部时钟信号的内部时钟信号的延迟锁定环路包括：用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测器; 延迟单元控制器，用于响应于相位检测器的输出信号产生控制信号和选择信号; 可变延迟装置（VDD），响应于控制信号和选择信号，在VDD输出线上产生外部时钟信号的延迟版本，该可变延迟装置被配置为使得如果外部时钟信号经历 从第一频率改变到与第一频率显着不同的第二频率，则VDD输出线上的合成负载仍然保持基本相同。

    Delay locked loop
    2.
    发明授权
    Delay locked loop 有权
    延迟锁定环路

    公开(公告)号：US07554371B2

    公开(公告)日：2009-06-30

    申请号：US11412803

    申请日：2006-04-28

    申请人： Jun-Bae Kim ,  Hyun-Ju Lee

    发明人： Jun-Bae Kim ,  Hyun-Ju Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

    摘要翻译： 用于产生锁定到外部时钟信号的内部时钟信号的延迟锁定环路包括：用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测器; 延迟单元控制器，用于响应于相位检测器的输出信号产生控制信号和选择信号; 可变延迟装置（VDD），响应于控制信号和选择信号，在VDD输出线上产生外部时钟信号的延迟版本，该可变延迟装置被配置为使得如果外部时钟信号经历 从第一频率改变到与第一频率显着不同的第二频率，则VDD输出线上的合成负载仍然保持基本相同。

    Semiconductor device and method of arranging pad thereof
    3.
    发明授权
    Semiconductor device and method of arranging pad thereof 有权
    半导体装置及其配置方法

    公开(公告)号：US07696626B2

    公开(公告)日：2010-04-13

    申请号：US11304226

    申请日：2005-12-15

    申请人： Young-Ok Cho ,  Jun-Bae Kim ,  Chan-Hee Jeon

    发明人： Young-Ok Cho ,  Jun-Bae Kim ,  Chan-Hee Jeon

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method of forming a pad thereof are provided. The device includes: a substrate; at least one first active region disposed in a first region of the substrate; at least one second active region disposed in a second region adjacent to the first region of the substrate; a plurality of first contacts disposed on the second active region; a first insulating layer disposed on the first active region and between the first contacts; a poly layer disposed on the first contacts and the first insulating layer; a plurality of second contacts disposed on the poly layer in the second region; a second insulating layer disposed between the second contacts and on the poly layer in the first region; and a pad disposed on the second insulating layer and the second contacts.

    摘要翻译： 提供一种半导体器件及其衬垫的形成方法。 该装置包括：基板; 设置在所述基板的第一区域中的至少一个第一有源区; 至少一个第二有源区域，设置在与所述衬底的所述第一区域相邻的第二区域中; 设置在所述第二有源区上的多个第一触点; 第一绝缘层，设置在第一有源区上和第一触点之间; 设置在所述第一触点和所述第一绝缘层上的多晶硅层; 设置在所述第二区域中的所述多层上的多个第二触点; 第二绝缘层，设置在所述第二触点之间并且在所述第一区域中的所述多晶硅层上; 以及设置在所述第二绝缘层和所述第二触点上的焊盘。

    DUTY CORRECTING CIRCUIT, DELAY-LOCKED LOOP CIRCUIT AND METHOD OF CORRECTING DUTY
    4.
    发明申请
    DUTY CORRECTING CIRCUIT, DELAY-LOCKED LOOP CIRCUIT AND METHOD OF CORRECTING DUTY 有权
    负载校正电路，延迟锁定环路和校正方法

    公开(公告)号：US20110298513A1

    公开(公告)日：2011-12-08

    申请号：US13078151

    申请日：2011-04-01

    申请人： Tae-Sik Na ,  Jun-Bae Kim

    发明人： Tae-Sik Na ,  Jun-Bae Kim

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

    摘要翻译： 占空比校正电路包括占空比校正器，占空比检测器和占空比校正码发生器。 占空比校正器校正输入时钟信号的占空比以产生输出时钟信号。 占空比检测器调节输出时钟信号的延迟时间以产生采样时钟信号，响应于采样时钟信号采样输出时钟信号以产生采样数据，并且基于逻辑状态检测输出时钟信号的占空比 样本数据。 因此，占空比校正电路精确地检测并校正输出时钟信号的占空比。

    DELAY LOCKED LOOP CIRCUITS AND METHOD FOR CONTROLLING THE SAME
    5.
    发明申请
    DELAY LOCKED LOOP CIRCUITS AND METHOD FOR CONTROLLING THE SAME 失效
    延迟锁定环路及其控制方法

    公开(公告)号：US20080169852A1

    公开(公告)日：2008-07-17

    申请号：US11969434

    申请日：2008-01-04

    申请人： Jun-Bae Kim ,  Chang-Hyung Bae

    发明人： Jun-Bae Kim ,  Chang-Hyung Bae

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/10

    摘要： A delay locked loop circuit and a method for controlling the same including a delay locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal synchronized to the external clock signal includes at least two delay chains having different types of delay cells for delaying the external clock signal. Thus, the layout area and power consumption can be reduced, and logic failures can be prevented or minimized by replacement or compensation of the main delay cells.

    摘要翻译： 一种延迟锁定环路电路及其控制方法，包括用于接收外部时钟信号并产生与外部时钟信号同步的内部时钟信号的延迟锁定环路（DLL）电路，包括至少两个具有不同延迟类型的延迟链 用于延迟外部时钟信号的单元。 因此，可以减少布局面积和功耗，并且可以通过主延迟单元的更换或补偿来防止或最小化逻辑故障。

    Semiconductor memory device for controlling operation of delay-locked loop circuit
    6.
    发明授权
    Semiconductor memory device for controlling operation of delay-locked loop circuit 有权
    用于控制延迟锁定环路电路的半导体存储器件

    公开(公告)号：US08730751B2

    公开(公告)日：2014-05-20

    申请号：US13467188

    申请日：2012-05-09

    申请人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

    发明人： Jun-Bae Kim ,  Seong-Jin Jang ,  Young-Uk Chang ,  Sin-Ho Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/222 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/0891

    摘要： A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

    摘要翻译： 提供一种用于控制延迟锁定环（DLL）电路的操作的半导体存储器件。 半导体存储器件包括DLL电路，其接收外部时钟信号，并且对外部时钟信号和内部时钟信号执行锁定操作，由此获得锁定状态。 控制单元控制DLL电路在刷新存储体的自动刷新操作的自动刷新周期的更新周期期间始终保持锁定状态。

    Duty correcting circuit, delay-locked loop circuit and method of correcting duty
    7.
    发明授权
    Duty correcting circuit, delay-locked loop circuit and method of correcting duty 有权
    负责校正电路，延迟锁定环路电路及其校正方法

    公开(公告)号：US08542045B2

    公开(公告)日：2013-09-24

    申请号：US13078151

    申请日：2011-04-01

    申请人： Tae-Sik Na ,  Jun-Bae Kim

    发明人： Tae-Sik Na ,  Jun-Bae Kim

    IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

    CPC分类号： H03K5/1565

    摘要： The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

    摘要翻译： 占空比校正电路包括占空比校正器，占空比检测器和占空比校正码发生器。 占空比校正器校正输入时钟信号的占空比以产生输出时钟信号。 占空比检测器调节输出时钟信号的延迟时间以产生采样时钟信号，响应于采样时钟信号采样输出时钟信号以产生采样数据，并且基于逻辑状态检测输出时钟信号的占空比 样本数据。 因此，占空比校正电路精确地检测并校正输出时钟信号的占空比。

    Semiconductor device and method of arranging pad thereof
    8.
    发明申请
    Semiconductor device and method of arranging pad thereof 有权
    半导体装置及其配置方法

    公开(公告)号：US20060131739A1

    公开(公告)日：2006-06-22

    申请号：US11304226

    申请日：2005-12-15

    申请人： Young-Ok Cho ,  Jun-Bae Kim ,  Chan-Hee Jeon

    发明人： Young-Ok Cho ,  Jun-Bae Kim ,  Chan-Hee Jeon

    IPC分类号： H01L23/34

    CPC分类号： H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method of forming a pad thereof are provided. The device includes: a substrate; at least one first active region disposed in a first region of the substrate; at least one second active region disposed in a second region adjacent to the first region of the substrate; a plurality of first contacts disposed on the second active region; a first insulating layer disposed on the first active region and between the first contacts; a poly layer disposed on the first contacts and the first insulating layer; a plurality of second contacts disposed on the poly layer in the second region; a second insulating layer disposed between the second contacts and on the poly layer in the first region; and a pad disposed on the second insulating layer and the second contacts.

    摘要翻译： 提供一种半导体器件及其衬垫的形成方法。 该装置包括：基板; 设置在所述基板的第一区域中的至少一个第一有源区; 至少一个第二有源区域，设置在与所述衬底的所述第一区域相邻的第二区域中; 设置在所述第二有源区上的多个第一触点; 第一绝缘层，设置在所述第一有源区上和所述第一触点之间; 设置在所述第一触点和所述第一绝缘层上的多晶硅层; 设置在所述第二区域中的所述多层上的多个第二触点; 第二绝缘层，设置在所述第二触点之间并且在所述第一区域中的所述多晶硅层上; 以及设置在所述第二绝缘层和所述第二触点上的焊盘。

    Optical baffling device
    9.
    发明授权
    Optical baffling device 失效
    光学挡板装置

    公开(公告)号：US5379081A

    公开(公告)日：1995-01-03

    申请号：US220799

    申请日：1994-03-31

    申请人： Jun-Bae Kim ,  Seong-Woo Nam

    发明人： Jun-Bae Kim ,  Seong-Woo Nam

    IPC分类号： G03B21/00 ,  G02B5/04 ,  G02B26/08 ,  G03B21/28 ,  H04N9/31

    CPC分类号： H04N9/315 ,  G02B26/0833 ,  G02B5/045

    摘要： An improved optical baffling device for use with an optical projection system has a base; a plurality of flat reflective surfaces of an equal size on a corresponding member of reflectors mounted on the base, the reflective surfaces being substantially parallel to each other; and the corresponding number of slits disposed in an alternating relationship with the reflective surfaces. A fraction of light from a light source is focused on each of the reflective surfaces and transmitted to a projection screen through a corresponding slit of the optical baffling device. Sine a fraction of light is processed separately, it becomes possible to enhance the optical efficiency of the optical projection system with a reduced amount of modulation of the optical path.

    摘要翻译： 用于光学投影系统的改进的光学挡板装置具有基座; 在安装在基座上的反射器的相应构件上具有相同尺寸的多个平坦反射表面，反射表面基本上彼此平行; 以及与反射表面交替关系设置的相应数量的狭缝。 来自光源的一小部分光聚焦在每个反射表面上，并通过光学挡板装置的相应狭缝传输到投影屏幕。 正确的一部分光被单独处理，可以以减小的光路调制量来增强光学投影系统的光学效率。