公开(公告)号：US20140038426A1

公开(公告)日：2014-02-06

申请号：US13956273

申请日：2013-07-31

Applicant: Globalfoundries Inc. ,  IMEC

Inventor： David Brunco ,  Geert Eneman

IPC: H01L21/02

CPC classification number: H01L21/02565 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/7843

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract translation: 公开了一种用于在制造期间减少半导体器件的有源器件区域中的缺陷的方法。 在一个方面，该方法包括提供邻近隔离结构的有源器件区域，其中基本平坦的表面形成在隔离结构和有源器件区域之上，在基本平坦的表面上形成图案化的应力诱导层，至少形成 在图案化的应力诱导层和基本上平坦的表面之间的一个屏蔽层，其中屏蔽层被配置为屏蔽由图案化的应力诱导层感应的应力场的一部分，在形成图案化的应力诱导层之后执行退火工艺 在基本上平坦的表面上，以引起缺陷朝向有源器件区域和隔离结构之间的接触界面的移动，以及从基本平坦的表面移除图案化的应力诱导层。