公开(公告)号：US20240363439A1

公开(公告)日：2024-10-31

申请号：US18770861

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US20240347377A1

公开(公告)日：2024-10-17

申请号：US18754653

申请日：2024-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Pu-Fang Chen ,  Cheng-Ta Wu ,  Po-Jung Chiang ,  Ru-Liang Lee ,  Victor Y. Lu ,  Yen-Hsiu Chen ,  Yeur-Luen Tu ,  Yu-Lung Yeh ,  Shi-Chieh Lin

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/84

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/84 ,  H01L21/26506

摘要： Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

公开(公告)号：US20240347339A1

公开(公告)日：2024-10-17

申请号：US18301493

申请日：2023-04-17

申请人： Syrnatec, Inc.

发明人： Yash Suresh Mirchandani ,  Nishita Suresh Mirchandani ,  Alexander Usenko

IPC分类号： H01L21/18 ,  B24B37/11 ,  H01L21/02 ,  H01L21/04 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/324 ,  H01L21/67 ,  H01L23/14

CPC分类号： H01L21/185 ,  B24B37/11 ,  H01L21/02378 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/0445 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/67075 ,  H01L21/67098 ,  H01L23/147

摘要： Methods and systems for making a composite substrate is provided. The method includes depositing a silicon layer on a surface of a silicon carbide wafer. The method includes smoothing the deposited silicon layer by Chemical Mechanical Polishing (CMP) and first annealing to produce a flat silicon surface on the silicon carbide wafer. The method includes bonding the flat silicon surface of the silicon carbide wafer with a gallium oxide wafer. The method includes second annealing the bonded silicon carbide wafer and gallium oxide wafer. The method includes thinning the bonded gallium oxide wafer to a thickness of about 2 to about 25 microns.

公开(公告)号：US20240339361A1

公开(公告)日：2024-10-10

申请号：US18620327

申请日：2024-03-28

申请人： Infineon Technologies AG

发明人： Franz-Josef Pichler ,  Benjamin Bernard ,  Mario Stefenelli

IPC分类号： H01L21/82 ,  H01L21/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/324 ,  H01L21/683 ,  H01L29/16

CPC分类号： H01L21/8213 ,  H01L21/02118 ,  H01L21/268 ,  H01L21/304 ,  H01L21/324 ,  H01L21/6836 ,  H01L29/1608 ,  H01L2221/68309 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A method for separating dies from a semiconductor substrate having dies adjoining a first surface of the substrate includes: attaching the substrate to a carrier via the first surface; generating first modifications by introducing laser irradiation into an interior of the substrate via a second surface of the substrate, the first modifications extending between the first surface and a vertical level in the interior that is being spaced from the second surface, the first modifications laterally surrounding the dies; generating second modifications by introducing laser irradiation into the interior via the second surface, the second modifications sub-dividing the substrate into a first part between the first surface and the second modifications, and a second part between the second surface and the second modifications; separating the parts along a first separation area defined by the second modifications; and separating the dies along a second separation area defined by the first modifications.

公开(公告)号：US20240339324A1

公开(公告)日：2024-10-10

申请号：US18131321

申请日：2023-04-05

申请人： Applied Materials, Inc.

发明人： Banqiu WU ,  Khalid MAKHAMREH ,  Eliyahu Shlomo DAGAN

IPC分类号： H01L21/265 ,  H01L21/324

CPC分类号： H01L21/26513 ,  H01L21/324

摘要： Methods and apparatus for contacting a substrate with a plasma at a pressure from about 300 Torr to about 1000 Torr for a period of time sufficient to heat a top portion of the substrate having a depth of less than about 200 nm, to a temperature high enough for annealing, and the temperature of the substrate at a depth of greater than or equal to about 200 nm is less than or equal to about 450° C.

公开(公告)号：US20240321953A1

公开(公告)日：2024-09-26

申请号：US18734605

申请日：2024-06-05

申请人： Infineon Technologies Austria AG

发明人： Hans Weber ,  Ingo Muri ,  Daniel Tutuc

IPC分类号： H01L29/06 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/7827 ,  H01L21/223 ,  H01L21/30604 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/7813

摘要： A superjunction transistor device includes a drift region with a plurality of first regions of a first doping type and a plurality of second regions of a second type in a semiconductor body. The first regions and the second regions are arranged alternately in the semiconductor body. The second regions include wide regions having a first width and narrow regions having a second width. The wide regions and the narrow regions are arranged alternately. The first width is at least 1.05 times the second width.

公开(公告)号：US20240304471A1

公开(公告)日：2024-09-12

申请号：US18666710

申请日：2024-05-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Wen WU ,  Chun-Ta CHEN ,  Chin-Shen HSIEH ,  Cheng-Yi HUANG

IPC分类号： H01L21/67 ,  F27B17/00 ,  F27D3/00 ,  F27D5/00 ,  H01L21/324

CPC分类号： H01L21/67103 ,  F27B17/0025 ,  F27D3/0084 ,  F27D5/0037 ,  H01L21/324

摘要： In an embodiment, an apparatus comprising: a heater configured to heat a wafer located on a wafer staging area of the heater, the heater comprising a heater shaft extending below the wafer staging area; and a heater lift assembly comprising: a lift shaft configured to move the heater shaft in a vertical direction; a clamp that connects the heater shaft to the lift shaft; and a damper disposed on top of the clamp.

公开(公告)号：US12087844B2

公开(公告)日：2024-09-10

申请号：US18356062

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20240290630A1

公开(公告)日：2024-08-29

申请号：US18521569

申请日：2023-11-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei Ying Lai ,  Cheng-Chieh Lin ,  Hsueh-Ju Chen ,  Tsung-Da Lin ,  Cheng-Hao Hou ,  Chi On Chui

IPC分类号： H01L21/324 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L21/324 ,  H01L21/823807 ,  H01L25/074 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： Dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. The dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. The nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon. Masked gate dielectrics without the dipole dopant source layer formed thereon remain undoped.

公开(公告)号：US20240258402A1

公开(公告)日：2024-08-01

申请号：US18629967

申请日：2024-04-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-HAN LIN ,  TE-AN CHEN

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L29/66143 ,  H01L21/02063 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28537 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/47 ,  H01L29/872

摘要： A method of manufacturing a Schottky barrier diode includes: forming a first well region and a second well region adjacent to the first well region in a substrate; depositing a first dielectric layer over the first well region and the second well region; performing a first patterning operation on the first dielectric layer to cause the first dielectric layer to include a stepped shape; performing a second patterning operation on the first dielectric layer to form a gate dielectric layer of a first transistor device in the second well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface.