公开(公告)号：US20240250115A1

公开(公告)日：2024-07-25

申请号：US18287939

申请日：2022-03-30

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Takenori WATABE ,  Hiroshi HASHIGAMI ,  Takahiro SAKATSUME

IPC: H01L29/04 ,  C30B25/16 ,  C30B25/18 ,  C30B29/16 ,  H01L21/02

CPC classification number: H01L29/04 ,  C30B25/16 ,  C30B25/18 ,  C30B29/16 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02565 ,  H01L21/0262

Abstract: A laminated structure including, a ground substrate with a crystalline oxide film containing gallium oxide as a main component and a root-mean-square of a roughness on a surface of the crystalline oxide film is 0.2 μm or less. A diameter of the ground substrate is 50 mm or more and TTV of the ground substrate is 30 μm or less.

公开(公告)号：US12046478B2

公开(公告)日：2024-07-23

申请号：US17669525

申请日：2022-02-11

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Luguang Wang ,  Xiaoling Wang

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/31111 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02634 ,  H01L21/76898 ,  H01L21/30655 ,  H01L21/3081

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided; the substrate is etched to form a blind hole, a sidewall of the blind hole has a first roughness; at least one planarization process is performed on the sidewall of the blind hole until the sidewall of the blind hole has a preset roughness less than the first roughness. The planarization process includes: a first sacrificial layer is formed on the sidewall of the blind hole; a reaction source gas is provided such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer; and the second sacrificial layer is removed, and after the second sacrificial layer is removed, the sidewall of the blind hole has a second roughness less than the first roughness.

公开(公告)号：US11830734B2

公开(公告)日：2023-11-28

申请号：US17324352

申请日：2021-05-19

Applicant: Applied Materials, Inc.

Inventor： Huiyuan Wang ,  Susmit Singha Roy ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/02532 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02612 ,  H01L21/02658 ,  H01L21/3205

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.

公开(公告)号：US11688625B2

公开(公告)日：2023-06-27

申请号：US17461338

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Kai Hsiao ,  Tsai-Yu Huang ,  Hui-Cheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02667

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

公开(公告)号：US20190252201A1

公开(公告)日：2019-08-15

申请号：US16391006

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Tsz-Mei Kwok

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/36 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08

CPC classification number: H01L21/31111 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02664 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/36 ,  H01L29/41783

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.

公开(公告)号：US20190229190A1

公开(公告)日：2019-07-25

申请号：US16231225

申请日：2018-12-21

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： T. Warren Weeks, JR. ,  Edwin Lanier Piner ,  Thomas Gehrke ,  Kevin J. Linthicum

IPC: H01L29/15 ,  H01L29/205 ,  H01L21/02 ,  H01L33/04 ,  C30B23/02 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L33/06 ,  H01L29/778 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/201 ,  H01L29/66 ,  H01L33/12 ,  H01L33/00 ,  H01L29/20 ,  H01L29/225 ,  H01L33/32 ,  C30B29/40 ,  C30B25/02

CPC classification number: H01L29/155 ,  C30B23/02 ,  C30B23/025 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/06 ,  C30B29/403 ,  C30B29/406 ,  C30B29/68 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/265

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

公开(公告)号：US20190081209A1

公开(公告)日：2019-03-14

申请号：US16190529

申请日：2018-11-14

Applicant: NICHIA CORPORATION

Inventor： Atsuo MICHIUE

IPC: H01L33/18 ,  H01L21/02 ,  H01L33/32 ,  H01L33/00 ,  H01L33/20 ,  H01L33/24 ,  H01L33/12 ,  H01L33/16

CPC classification number: H01L33/18 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/16 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32

Abstract: A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of InXAlYGa1−X−YN (0≤X, 0≤Y, X+Y

公开(公告)号：US20190057986A1

公开(公告)日：2019-02-21

申请号：US15578562

申请日：2017-10-13

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD

Inventor： Tao Wang

IPC: H01L27/12 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L27/1274 ,  H01L21/0243 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/2855 ,  H01L21/32133 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1262 ,  H01L29/66757 ,  H01L29/78672 ,  H01L29/78675

Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.

公开(公告)号：US20180337034A1

公开(公告)日：2018-11-22

申请号：US15598439

申请日：2017-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying LEE ,  Shao-Ming YU

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/34

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/34

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.

公开(公告)号：US10074773B2

公开(公告)日：2018-09-11

申请号：US15671275

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae In Sim ,  Ju Heon Yoon ,  Gi Bum Kim ,  Ji Hye Lee

IPC: H01L33/36 ,  H01L33/22 ,  H01L21/02 ,  H01L33/00 ,  H01L33/38 ,  H01L33/42

CPC classification number: H01L33/22 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L33/007 ,  H01L33/38 ,  H01L33/42 ,  H01L33/486 ,  H01L33/60 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2933/0016 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor light emitting device includes a light emitting structure in which a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer are sequentially laminated, an insulating layer disposed on the light emitting structure and including first and second openings, an electrode layer disposed on the insulating layer and including first and second electrodes, and an adhesive layer disposed between the electrode layer and the insulating layer and including first and second openings. The first opening of the adhesive layer overlaps the first opening of the insulating layer and is equal to or larger than the first opening of the insulating layer. The second opening of the adhesive layer overlaps the second opening of the insulating layer and is equal to or larger than the second opening of the insulating layer.