公开(公告)号：US20180197966A1

公开(公告)日：2018-07-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/78

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US10008445B2

公开(公告)日：2018-06-26

申请号：US15110704

申请日：2014-02-11

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/78 ,  H01L21/768 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/525 ,  H01L27/112 ,  H01L29/66

CPC classification number: H01L23/5256 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embedded fuse structures and fabrication techniques. An embedded fuse may include a non-planar conductive line having two high-z portions extending to a greater z-height than a low-z portion of reduced current carrying capability disposed there between. A dielectric disposed over the low-z portion has a top surface planar with the high-z line portions to which fuse contacts may be landed. Fabrication of an embedded fuse may include undercutting a region of a first dielectric material disposed over a substrate. The undercut region is lined with a second dielectric material. A pair of electrically joined fuse ends are formed by backfilling the lined undercut region with a conductive material. In advantageous embodiments, fuse fabrication is compatible with high-K, metal gate transistor and precision polysilicon resistor fabrication flows.

公开(公告)号：US09324665B2

公开(公告)日：2016-04-26

申请号：US14142629

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/62 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/525

CPC classification number: H01L23/62 ,  H01L21/0217 ,  H01L21/32055 ,  H01L23/5256 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。 在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。 隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。 隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。 可以描述和/或要求保护其他实施例。