公开(公告)号：US11532706B2

公开(公告)日：2022-12-20

申请号：US16369760

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Siddharth Chouksey

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/32 ,  H01L29/165 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/027 ,  H01L21/66

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20200227558A1

公开(公告)日：2020-07-16

申请号：US16637213

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anand Murthy ,  Karthik Jambunathan ,  Cory Bomberger

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8234

Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.

公开(公告)号：US20200091287A1

公开(公告)日：2020-03-19

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.