公开(公告)号：US10020931B2

公开(公告)日：2018-07-10

申请号：US13789241

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Mohamed A. Abdelmoneum ,  Nasser A. Kurd ,  Amr M. Lotfy ,  Mamdouh O. Abd El-Mejeed ,  Mohamed A. Abdelsalam

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/099

CPC classification number: H04L7/0331 ,  H03L7/0995 ,  H04L7/033

Abstract: Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.