公开(公告)号：US11424239B2

公开(公告)日：2022-08-23

申请号：US16724257

申请日：2019-12-21

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid ,  Veronica Aleman Strong ,  Johanna M. Swan

IPC: H01L27/02 ,  H01L29/872

Abstract: Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

公开(公告)号：US20220181276A1

公开(公告)日：2022-06-09

申请号：US17677877

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H01L23/48 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US11289431B2

公开(公告)日：2022-03-29

申请号：US16728127

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/495 ,  H01L23/60 ,  H01L23/498 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.

公开(公告)号：US11264373B2

公开(公告)日：2022-03-01

申请号：US16724259

申请日：2019-12-21

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid ,  Veronica Aleman Strong ,  Johanna M. Swan

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/24 ,  H01L29/861 ,  H01L29/47 ,  H01L29/872 ,  H01L29/45

Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

公开(公告)号：US11147197B2

公开(公告)日：2021-10-12

申请号：US16659459

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid

IPC: H05K9/00 ,  H01L23/60 ,  H01L21/48 ,  C08G61/12 ,  C08G73/06 ,  C08G85/00 ,  H01L23/498

Abstract: Embodiments may relate to a material to provide electrostatic discharge (ESD) protection in an electrical device. The material may include first and second electrically-conductive carbon allotropes. The material may further include an electrically-conductive polymer that is chemically bonded to the first and second electrically-conductive carbon allotropes such that an electrical signal may pass between the first and second electrically-conductive carbon allotropes. Other embodiments may be described or claimed.

公开(公告)号：US20210287979A1

公开(公告)日：2021-09-16

申请号：US16817309

申请日：2020-03-12

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Henning Braunisch ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498

Abstract: Embodiments may relate to a microelectronic package with an interconnect stack that includes a cavity therein. The cavity may include a dielectric material with a dielectric value less than 3.9. The microelectronic package may further include first and second conductive elements in the cavity, with the dielectric material positioned therebetween. Other embodiments may be described or claimed.