公开(公告)号：US11704564B2

公开(公告)日：2023-07-18

申请号：US17404153

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

CPC classification number: G06N3/08 ,  G06N20/00 ,  G06N20/10

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US11620766B2

公开(公告)日：2023-04-04

申请号：US17344639

申请日：2021-06-10

Applicant: INTEL CORPORATION

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00 ,  H04N19/42 ,  G06N3/04 ,  H04N19/436 ,  G06N3/084 ,  G06N3/088

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer.

公开(公告)号：US11599777B2

公开(公告)日：2023-03-07

申请号：US15499900

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/00 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US11494608B2

公开(公告)日：2022-11-08

申请号：US16540581

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Moshe Maor

IPC: G06N3/02 ,  G06N3/04 ,  G06F17/15 ,  G06F8/41 ,  G06N3/063

Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.

公开(公告)号：US20220067496A1

公开(公告)日：2022-03-03

申请号：US17398302

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US11250610B2

公开(公告)日：2022-02-15

申请号：US17006253

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/02 ,  G06T15/00 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US11132601B2

公开(公告)日：2021-09-28

申请号：US15494887

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US10990399B2

公开(公告)日：2021-04-27

申请号：US16539005

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Moshe Maor ,  Yaniv Fais

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/38

Abstract: Methods and apparatus to implement efficient communications between components of computing systems are disclosed. An example apparatus includes a message generator to: add a first value associated with a first field of a message to a shift register based on a first push operation, the message including multiple fields, at least two of the fields having different bit widths; and add a second value associated with a second field of the message to the shift register based on a second push operation, the second value to be adjacent the first value in the shift register in accordance with a structure of the message. The example apparatus further includes a communications interface to transmit content stored in the shift register to a hardware device via a bus having a width corresponding to a width of the shift register, the content including the message.

公开(公告)号：US10467795B2

公开(公告)日：2019-11-05

申请号：US15482724

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/02 ,  G06T15/00 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314492A1

公开(公告)日：2018-11-01

申请号：US15499893

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N99/00

CPC classification number: G06F7/5332 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.