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公开(公告)号：US12223413B2
公开(公告)日：2025-02-11
申请号：US18392761
申请日：2023-12-21
Applicant: Intel Corporation
Inventor： Yaniv Fais , Moshe Maor
Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
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公开(公告)号：US20250045560A1
公开(公告)日：2025-02-06
申请号：US18922038
申请日：2024-10-21
Applicant: Intel Corporation
Inventor： Yaniv Fais , Moshe Maor
Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
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3.发明授权公开(公告)号：US09898286B2
公开(公告)日：2018-02-20
申请号：US14704633
申请日：2015-05-05
Applicant: INTEL CORPORATION
Inventor： Edwin Jan Van Dalen , Martinus C. Wezelenburg , Steven Roos , Edward T. Grochowski , Moshe Maor
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/3893 , G06F9/455 , H03H17/0202 , H03H17/06 , H03H2017/0298
Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.
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公开(公告)号：US09705916B2
公开(公告)日：2017-07-11
申请号：US13629965
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Omer Ben-Shalom , Alex Nayshtut , Moshe Maor
CPC classification number: H04L63/164 , H04L63/18 , H04L69/32
Abstract: Systems and methods may provide for establishing an out-of-band (OOB) channel between a local wireless interface and a remote backend receiver, and receiving information from a peripheral device via the local wireless interface. Additionally, the information may be sent to the backend receiver via the OOB channel, wherein the OOB channel bypasses a local operating system. In one example, a secure Bluetooth stack is used to receive the information from the peripheral device.
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公开(公告)号：US12217101B2
公开(公告)日：2025-02-04
申请号：US18309650
申请日：2023-04-28
Applicant: INTEL CORPORATION
Inventor： Michael Behar , Moshe Maor , Ronen Gabbai , Roni Rosner , Zigi Walter , Oren Agam
IPC: G06F9/50 , G06F16/901 , G06N3/044 , G06N3/045
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.
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Patent Agency Ranking
公开(公告)号：US20240119255A1
公开(公告)日：2024-04-11
申请号：US18392761
申请日：2023-12-21
Applicant: Intel Corporation
Inventor： Yaniv Fais , Moshe Maor
Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
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公开(公告)号：US11675630B2
公开(公告)日：2023-06-13
申请号：US16541979
申请日：2019-08-15
Applicant: Intel Corporation
Inventor： Michael Behar , Moshe Maor , Ronen Gabbai , Roni Rosner , Zigi Walter , Oren Agam
IPC: G06F9/50 , G06F16/901 , G06N3/044 , G06N3/045
CPC classification number: G06F9/5083 , G06F16/9024 , G06N3/044 , G06N3/045
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.
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8.发明申请PACKED FINITE IMPULSE RESPONSE (FIR) FILTER PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权包装有限冲突响应（FIR）过滤器，方法，系统和说明公开(公告)号：US20160328233A1
公开(公告)日：2016-11-10
申请号：US14704633
申请日：2015-05-05
Applicant: INTEL CORPORATION
Inventor： Edwin Jan Van Dalen , Martinus C. Wezelenburg , Steven Roos , Edward T. Grochowski , Moshe Maor
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/3893 , G06F9/455 , H03H17/0202 , H03H17/06 , H03H2017/0298
Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.
Abstract translation: 处理器包括解码单元，用于解码指示一个或多个源打包数据操作数，多个FIR滤波器系数和目的地存储位置的压缩有限脉冲响应（FIR）滤波器指令。 源操作数包括第一数量的数据元素和第二数量的附加数据元素。 第二个数字是少于FIR滤波器抽头的数量。 响应于被解码的打包FIR滤波器指令，执行单元是存储结果打包数据操作数。 结果打包数据操作数包括第一数量的FIR滤波数据元素，每个FIR滤波数据元素将基于多个FIR滤波器系数的乘积和来自一个或多个源打包数据操作数的不同对应的数据元素的组合， 其数量与FIR滤波器抽头的数量相等。
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公开(公告)号：US12112251B2
公开(公告)日：2024-10-08
申请号：US17954846
申请日：2022-09-28
Applicant: Intel Corporation
Inventor： Yaniv Fais , Moshe Maor
Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
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10.发明授权公开(公告)号：US11847497B2
公开(公告)日：2023-12-19
申请号：US17561500
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Michael Behar , Moshe Maor , Ronen Gabbai , Roni Rosner , Zigi Walter , Oren Agam
CPC classification number: G06F9/5016 , G06F3/0613 , G06F3/0659 , G06F3/0673 , G06F9/505
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.
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