公开(公告)号：US20220068750A1

公开(公告)日：2022-03-03

申请号：US17090921

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jackson Chung Peng KONG

IPC: H01L23/367 ,  H01L23/538

Abstract: A device including a package substrate and a heat spreader may be provided. The package substrate may include a first surface and an opposing second surface. The package substrate may include a recess extending from the first surface, and a cavity extending from the second surface to the recess. The heat spreader may include a first portion and a second portion arranged on the first portion. The first portion may be arranged within the cavity, and the second portion may be at least partially arranged on the second surface of the package substrate

公开(公告)号：US20220068740A1

公开(公告)日：2022-03-03

申请号：US17088621

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/14 ,  H01R12/71

Abstract: According to various examples, a device is described. The device may include a printed circuit board. The device may include a semiconductor package including an interposer with a molded portion, and one or more of semiconductor devices. The one or more semiconductor devices may have at least a first device coupled to the molded portion. The device may include a first connector coupled to the molded portion, and a second connector coupled to the printed circuit board, the first connector and the second connector configured to be connected with a cable for signal connection between the first device and the printed circuit board.

公开(公告)号：US20210410273A1

公开(公告)日：2021-12-30

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM ,  Chin Lee KUAN ,  Tin Poay CHUAH

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US20210335718A1

公开(公告)日：2021-10-28

申请号：US17368837

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board.