公开(公告)号：US20240145450A1

公开(公告)日：2024-05-02

申请号：US18050527

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Amit JAIN ,  Sameer SHEKHAR

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.

公开(公告)号：US20190158024A1

公开(公告)日：2019-05-23

申请号：US16237093

申请日：2018-12-31

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

CPC classification number: H03B5/32 ,  H03B2200/0088 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20210410273A1

公开(公告)日：2021-12-30

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Seok Ling LIM ,  Chin Lee KUAN ,  Tin Poay CHUAH

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US20210384135A1

公开(公告)日：2021-12-09

申请号：US16987440

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Sameer SHEKHAR ,  Amit JAIN

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

公开(公告)号：US20220199551A1

公开(公告)日：2022-06-23

申请号：US17129838

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Amit Kumar JAIN ,  Sameer SHEKHAR ,  Telesphor KAMGAING ,  Chin Lee KUAN ,  Vivek SAXENA

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/64 ,  H01L49/02 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages with stiffeners. In an embodiment, a stiffener for an electronic package comprises a first layer, that is conductive, and a second layer over the first layer, where the second layer is insulative. In an embodiment, the stiffener further comprises a third layer over the second layer, where the third layer is conductive. In an embodiment, the stiffener further comprises a leg attached to the third layer, where the leg extends towards the first layer and is substantially coplanar with a surface of the first layer opposite from the second layer.

公开(公告)号：US20200051884A1

公开(公告)日：2020-02-13

申请号：US16059513

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Sameer SHEKHAR ,  Amit Kumar JAIN ,  Kaladhar RADHAKRISHNAN ,  Jonathan P. DOUGLAS ,  Chin Lee KUAN

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  G06F1/20

Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

公开(公告)号：US20190304923A1

公开(公告)日：2019-10-03

申请号：US15939162

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Sameer SHEKHAR ,  Chin Lee KUAN ,  Amit Kumar JAIN

IPC: H01L23/552 ,  H01L23/00

Abstract: Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.

公开(公告)号：US20220077065A1

公开(公告)日：2022-03-10

申请号：US17089744

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/50 ,  H01L23/64 ,  H01L21/56 ,  H01L21/768

Abstract: A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.

公开(公告)号：US20210233875A1

公开(公告)日：2021-07-29

申请号：US17229316

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Tin Poay CHUAH ,  Chin Lee KUAN

IPC: H01L23/64 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H01L23/50

Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US20200274491A1

公开(公告)日：2020-08-27

申请号：US16714390

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Raymond CHONG ,  Ramaswamy PARTHASARATHY ,  Stephen HALL ,  Chin Lee KUAN

IPC: H03B5/32 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.