公开(公告)号：US20130085726A1

公开(公告)日：2013-04-04

申请号：US13251517

申请日：2011-10-03

申请人： Peter A. Habitz ,  Amol A. Joshi

发明人： Peter A. Habitz ,  Amol A. Joshi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.

摘要翻译： 方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。 方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。 方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

公开(公告)号：US20120124542A1

公开(公告)日：2012-05-17

申请号：US12944480

申请日：2010-11-11

申请人： Soroush Abbaspour ,  Peter Feldmann ,  Peter A. Habitz ,  Safar Hatami

发明人： Soroush Abbaspour ,  Peter Feldmann ,  Peter A. Habitz ,  Safar Hatami

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/80 ,  G06F2217/84

摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.

摘要翻译： 一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差 分支和第二分支横跨不同的过程电压温度值。

公开(公告)号：US08141014B2

公开(公告)日：2012-03-20

申请号：US12538229

申请日：2009-08-10

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

摘要翻译： 一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。 一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入 对当前段的信号具有有界历史，至少一个传播和断言。 该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

公开(公告)号：US08086988B2

公开(公告)日：2011-12-27

申请号：US12467326

申请日：2009-05-18

申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031

摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。

公开(公告)号：US07870525B2

公开(公告)日：2011-01-11

申请号：US12122451

申请日：2008-05-16

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

公开(公告)号：US20100327892A1

公开(公告)日：2010-12-30

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/02

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US07716616B2

公开(公告)日：2010-05-11

申请号：US11930924

申请日：2007-10-31

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

公开(公告)号：US20090265674A1

公开(公告)日：2009-10-22

申请号：US12103845

申请日：2008-04-16

申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Chandramouli Visweswariah

发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

摘要翻译： 识别数字设计中的故障定时要求的方法。 该方法包括识别数字设计中的至少一个定时测试，其在基本过程角落中具有通过松弛，并且在不同的过程角落中发生故障的松弛。 该方法还包括计算对于多个变量中的每一个的故障松弛的灵敏度，并将每个灵敏度与相应的灵敏度阈值进行比较。 如果至少一个变量的灵敏度大于相应的灵敏度阈值，则认为至少一个定时测试失败。

公开(公告)号：US20080195993A1

公开(公告)日：2008-08-14

申请号：US12107158

申请日：2008-04-22

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US07181711B2

公开(公告)日：2007-02-20

申请号：US10908101

申请日：2005-04-27

申请人： Eric A. Foreman ,  Peter A. Habitz ,  Gregory M. Schaeffer

发明人： Eric A. Foreman ,  Peter A. Habitz ,  Gregory M. Schaeffer

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.

摘要翻译： 一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。 优选地，随机噪声事件包括非时钟事件。 此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。 优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。