公开(公告)号：US07349277B2

公开(公告)日：2008-03-25

申请号：US11431371

申请日：2006-05-09

申请人： Thomas H. Kinsley ,  Jeffery W. Janzen

发明人： Thomas H. Kinsley ,  Jeffery W. Janzen

IPC分类号： G11C7/00

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

摘要： A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.

摘要翻译： 动态随机存取存储器件包括用延迟值编程的模式寄存器。 在一些实施例中，偏移代码也存储在存储器件中。 存储器件使用延迟值，该延迟值可以被添加到偏移代码或乘以偏移代码，以延迟接收的自动刷新或自刷新命令的启动。 可以为系统中的大量动态随机存取存储器件提供不同的延迟值和可能的偏移代码，使得存储器件不是都响应于自动刷新或自刷新命令而同时执行刷新 同时存储设备。 结果，由自动刷新命令或自刷新命令产生的存储器件所绘制的峰值电流保持在较低的值。

公开(公告)号：US07085912B2

公开(公告)日：2006-08-01

申请号：US10778257

申请日：2004-02-13

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F12/00

CPC分类号： G11C7/1033

摘要： Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.

摘要翻译： 操作由存储器单元的多个阵列和用于向存储器单元读取和写入信息的外围设备的存储器件的操作方法。 一种方法包括响应于地址位从多个存储器阵列输出两个1/2位预取步骤中的n位字。 另一种方法包括从存储器阵列预取字的第一部分，以及从存储器阵列预取字的第二部分，第一和第二部分由地址位确定。 另一种方法包括在至少两个预取操作中从存储器阵列中读出一个字，其中预取操作的顺序由地址位控制。

公开(公告)号：US06775759B2

公开(公告)日：2004-08-10

申请号：US10008710

申请日：2001-12-07

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F1200

CPC分类号： G11C7/1033

摘要： A memory device is comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may be a read address or a write address, and the order may be the order for reading data or writing data, respectively. The peripheral devices may also include a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be read or written in response to another portion of the address information. Methods of operating such a memory device including outputting or reading a word from a memory array in two prefetch steps or operations are also disclosed.

摘要翻译： 存储器装置由存储器单元的多个阵列和用于向存储器单元读取和写入信息的外围设备组成。 外围设备包括响应于用于识别地址的地址信息的第一部分的解码电路，并且还响应于用于识别订单的地址信息的第二部分。 该地址可以是读取地址或写入地址，并且该顺序可以分别是读取数据或写入数据的顺序。 外围设备还可以包括读序列器电路或写定序器电路和读定序器电路，用于根据地址信息的另一部分重新排序要读或写的位。 还公开了这样的存储装置的操作方法，包括在两个预取步骤或操作中从存储器阵列输出或读出一个字。

公开(公告)号：US08174858B2

公开(公告)日：2012-05-08

申请号：US12690790

申请日：2010-01-20

申请人： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

发明人： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

IPC分类号： G11C5/02

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/3275 ,  G11C5/04 ,  G11C7/04 ,  G11C7/20 ,  G11C2029/4402 ,  Y02D10/13 ,  Y02D10/14

摘要： Systems, memory modules and methods of configuring systems including memory modules are provided. The memory modules include device parameters specifically corresponding to memory devices of the memory module. The device parameters may be retrieved from a database, and the system may be configured in accordance with the device parameters retrieved from the database.

摘要翻译： 提供了系统，存储器模块和配置包括存储器模块的系统的方法。 存储器模块包括特别对应于存储器模块的存储器件的器件参数。 可以从数据库检索设备参数，并且可以根据从数据库检索的设备参数来配置系统。

公开(公告)号：US20120036314A1

公开(公告)日：2012-02-09

申请号：US13276592

申请日：2011-10-19

申请人： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

发明人： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

IPC分类号： G06F12/02

CPC分类号： G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

摘要： A system with a memory device having programmable elements used to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device is incorporated into a system. Once the memory device is incorporated into a system, the programmable elements may be accessed by a processor such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for the memory device in the system.

摘要翻译： 具有存储器件的系统具有用于配置存储器系统的可编程元件。 更具体地，位于存储器件上的诸如反熔丝的可编程元件在制造期间被编程，其中测量的操作参数对应于存储器件。 操作参数可以包括例如工作电流值，工作电压或时序参数。 存储器件被并入到系统中。 一旦存储器件被并入到系统中，可编程元件可以由处理器访问，使得存储器系统可以被配置为根据对系统中的存储器件测量的操作参数进行最佳操作。

公开(公告)号：US07590797B2

公开(公告)日：2009-09-15

申请号：US10822275

申请日：2004-04-08

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F13/40

CPC分类号： G06F13/1684 ,  G11C5/025 ,  G11C5/04

摘要： An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

摘要翻译： 装置和方法将存储器模块中的存储器件耦合到模块上的存储器集线器，使得从集线器传输到设备的信号具有大致相同的传播时间，而不管涉及哪个设备。 具体地，设备成对地布置在集线器周围，每对设备被定向成使得成对中的每个设备（例如数据总线信号）的功能信号组彼此相邻地定位在 模块。 这允许具有大致相同电特性的数据和控制地址总线在集线器和每个设备之间路由。 这种设备的物理布置允许模块的高速运行。 在一个示例中，集线器位于模块的中心，并且四个对设置在集线器周围的八个设备。

公开(公告)号：US07480792B2

公开(公告)日：2009-01-20

申请号：US11495964

申请日：2006-07-28

申请人： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

发明人： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

IPC分类号： G06F9/312 ,  G06F15/177

CPC分类号： G06F11/3037 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3058

摘要： Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating parameters for specific memory devices on the memory module or a specific lot in which the memory devices are fabricated may be stored on a non-volatile memory device on the memory module. A system may be configured in accordance with the operating parameters stored on the non-volatile memory device such that corresponding thresholds are not exceeded.

摘要翻译： 具有存储在其上的精确操作参数的存储器模块以及用于制造和实施这些设备以提高系统性能的方法。 可以制造包括多个易失性存储器件的存储器模块。 存储器模块或其中制造存储器件的特定批量的特定存储器件的操作参数可以存储在存储器模块上的非易失性存储器件上。 可以根据存储在非易失性存储设备上的操作参数来配置系统，使得不超过相应的阈值。

公开(公告)号：US07389369B2

公开(公告)日：2008-06-17

申请号：US11216672

申请日：2005-08-31

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F13/00

CPC分类号： G06F13/4086

摘要： A method and apparatus are provided for active termination control in a memory. In an embodiment, the memory turns on active termination based on information programmed into one or more mode registers of the memory. In an embodiment, the memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

摘要翻译： 提供了一种用于存储器中的主动终止控制的方法和装置。 在一个实施例中，存储器基于编程到存储器的一个或多个模式寄存器中的信息来开启有效终止。 在一个实施例中，存储器基于编程到存储器的一个或多个模式寄存器中的信息，将活动终端保持在接通状态达预定时间。

公开(公告)号：US07340584B2

公开(公告)日：2008-03-04

申请号：US11407780

申请日：2006-04-20

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F12/00

CPC分类号： G11C7/1033

摘要： A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word to be read or written. The decode circuit is further responsive to a second portion of the address information for identifying an order in which one or more portions of the identified word are to be read or written. An address sequencer routes at least one bit of the address information. A sequencer circuit is responsive to the address sequencer for ordering the plurality of data bits within each portion of the identified word.

摘要翻译： 用于存储器件的电路的组合包括一个响应于第一部分地址信息的解码电路，用于识别要被读或写的字。 解码电路还响应于地址信息的第二部分，用于识别所识别的字的一个或多个部分要被读取或写入的顺序。 地址定序器路由地址信息的至少一位。 定序器电路响应于地址定序器，用于对所识别的字的每个部分内的多个数据位进行排序。

公开(公告)号：US07277996B2

公开(公告)日：2007-10-02

申请号：US11417388

申请日：2006-05-03

申请人： Paul A. LaBerge ,  Jeffery W. Janzen

发明人： Paul A. LaBerge ,  Jeffery W. Janzen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C2207/2281 ,  G11C2207/229

摘要： A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method may be used in memory systems that infrequently experience page hits, such as server systems, while the ability to disable the persistent auto precharge mode allows such memory devices to be used in systems that frequently experience page hits, such as graphics or input/output applications.

摘要翻译： 一种操作存储器件的方法包括：将存储器件置于持续自动预充电操作模式中，对存储器件施加禁用命令，以及响应于应用的禁用命令禁用持续自动预充电操作模式。 根据这种方法运行的内存设备可能会用于经常遇到页面命中的内存系统（如服务器系统），而禁用持续自动预充电模式的功能允许将这种内存设备用于经常访问页面命中的系统，例如 图形或输入/输出应用程序。