公开(公告)号：US06673715B2

公开(公告)日：2004-01-06

申请号：US10002335

申请日：2001-10-24

申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Chi-Chen Cho

发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Chi-Chen Cho

IPC分类号： H01L2144

CPC分类号： H01L21/76888 ,  H01L21/76897

摘要： Methods of forming conductive contacts are described. According to one implementation, the method includes forming a transistor gate structure over a substrate. The gate structure includes a conductive silicide covered by insulative material. A dielectric layer is formed over the substrate and the gate structure. A contact opening is etched into the dielectric layer adjacent the gate structure. After the etching, the substrate is exposed to oxidizing conditions effective to oxidize any conductive silicide within the contact opening which was exposed during the contact opening etch. After the oxidizing, conductive material is formed within the contact opening. According to another embodiment, after the etching, it is determined whether conductive silicide of the gate structure was exposed during the etching. The substrate is then exposed to oxidizing conditions only if conductive silicide of the gate structure was exposed during the etching.

公开(公告)号：US08658506B1

公开(公告)日：2014-02-25

申请号：US13328912

申请日：2011-12-16

申请人： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

发明人： Zhongze Wang ,  Choh fei Yeap ,  Ping Liu

IPC分类号： H01L21/336

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/7833 ,  Y02D70/00

摘要： Methods and apparatus for selectively improving integrated circuit performance are provided. In an example, a method is provided that includes defining a critical portion of an integrated circuit layout that determines the speed of an integrated circuit, identifying at least a part of the critical portion that includes at least one of a halo, lightly doped drain (LDD), and source drain extension (SDE) implant region, and performing a speed push flow process to increase performance of the part of the critical portion that includes the at least one of the halo, the LDD, and the SDE implant region. The resultant integrated circuit can be integrated with a mobile device.

摘要翻译： 提供了选择性地提高集成电路性能的方法和装置。 在一个示例中，提供了一种方法，其包括限定集成电路布局的关键部分，该集成电路布局确定集成电路的速度，识别临界部分的至少一部分，其包括卤素，轻掺杂漏极（ LDD）和源极漏极扩展（SDE）注入区域，并且执行速度推动流程处理以增加包括所述晕圈，LDD和SDE植入区域中的至少一个的关键部分的部分的性能。 所得到的集成电路可以与移动设备集成。

公开(公告)号：US08279693B2

公开(公告)日：2012-10-02

申请号：US12757485

申请日：2010-04-09

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/419

摘要： One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking circuit comprises one or more columns of tracking cells. Each column is coupled to a corresponding bit line to provide a drive current on the bit line for triggering a memory read operation by the sense amplifier. At least one of the columns comprises two tracking cells connected in series to each other.

摘要翻译： 一个示例性存储器件包括存储器阵列，读出放大器和跟踪电路。 存储器阵列由多个存储单元形成。 读出放大器用于访问存储器阵列。 跟踪电路用于跟踪存储器阵列的存储器读取电流。 跟踪电路包括一列或多列跟踪单元。 每列耦合到对应的位线，以在位线上提供驱动电流，以触发读出放大器的存储器读取操作。 至少一列包括彼此串联连接的两个跟踪单元。

公开(公告)号：US07968954B2

公开(公告)日：2011-06-28

申请号：US11756922

申请日：2007-06-01

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28194

摘要： A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

摘要翻译： 提供了一种用于在掺杂剂注入和激活之后使用氮注入和退火来降低栅极氧化物的有效厚度的方法。 更具体地说，本发明提供一种用于制造半导体器件的方法，例如晶体管，其包括硬化的栅极氧化物，其特征可以在多晶硅/栅极氧化物界面处具有相对较大的氮浓度， 栅极氧化物和栅极氧化物/衬底界面处。 另外，本发明提供了一种用于制造半导体器件的方法，该半导体器件具有设置在其多晶硅层上的金属栅极带（例如，金属硅化物层），该器件包括硬化的栅极氧化物，并且其特征可以是相对较大的氮 在硅化物/多晶硅界面处的浓度基本上防止交叉扩散。

公开(公告)号：US20110140288A1

公开(公告)日：2011-06-16

申请号：US12638557

申请日：2009-12-15

申请人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

发明人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

IPC分类号： H01L23/50 ,  H01L21/3205

CPC分类号： H01L27/0207 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

摘要翻译： 一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。 集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。 导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。 导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

公开(公告)号：US20110121372A1

公开(公告)日：2011-05-26

申请号：US12624509

申请日：2009-11-24

申请人： Wootag Kang ,  Zhongze Wang

发明人： Wootag Kang ,  Zhongze Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10811 ,  H01L27/10897

摘要： A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area.

摘要翻译： 一种制造eDRAM器件的方法包括在半导体衬底上制造半导体器件，该半导体衬底包括一个DRAM区域和逻辑区域。 该工艺还包括在DRAM区域和逻辑区域中制造第一导电层，第一导电层与第一组半导体特征通信。 在制造第一导电层之后，制造与DRAM区域内的第二组半导体特征通信的存储部件。

公开(公告)号：US07259435B2

公开(公告)日：2007-08-21

申请号：US10985573

申请日：2004-11-10

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28194

摘要： A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

摘要翻译： 提供了一种用于在掺杂剂注入和激活之后使用氮注入和退火来降低栅极氧化物的有效厚度的方法。 更具体地说，本发明提供一种用于制造半导体器件的方法，例如晶体管，其包括硬化的栅极氧化物，其特征可以在多晶硅/栅极氧化物界面处具有相对较大的氮浓度， 栅极氧化物和栅极氧化物/衬底界面处。 另外，本发明提供了一种用于制造半导体器件的方法，该半导体器件具有设置在其多晶硅层上的金属栅极带（例如，金属硅化物层），该器件包括硬化的栅极氧化物，并且其特征可以是相对较大的氮 在硅化物/多晶硅界面处的浓度基本上防止交叉扩散。

公开(公告)号：US07154146B2

公开(公告)日：2006-12-26

申请号：US11283015

申请日：2005-11-18

申请人： Hongmei Wang ,  Zhongze Wang

发明人： Hongmei Wang ,  Zhongze Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

公开(公告)号：US20060076619A1

公开(公告)日：2006-04-13

申请号：US11283015

申请日：2005-11-18

申请人： Hongmei Wang ,  Zhongze Wang

发明人： Hongmei Wang ,  Zhongze Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

摘要翻译： 本发明提供了一种制造MOSFET中的电介质塞的技术。 本发明包括包括一个或多个器件的器件和系统，该器件和系统包括具有电介质插塞的MOSFET。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底，并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域 和漏区。

公开(公告)号：US07012293B2

公开(公告)日：2006-03-14

申请号：US10379480

申请日：2003-03-04

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The present invention provides an improved SRAM cell design. The SRAM cell includes a first active area on oxide in a first conductive well located on a first vertical side of the SRAM cell, a second active area on oxide in a second conductive well located on the first vertical side of the SRAM cell, a third active area on oxide in the first conductive well located on a second vertical side of the SRAM cell, a fourth active area on oxide in the second conductive well located on the second vertical side of the SRAM cell, a first gate located on the first vertical side of the SRAM cell, a second gate located on the second vertical side of the SRAM cell, a first local interconnect connecting the first active area, the second active area, and the second gate via a second EC contact located on the second gate, and a second local interconnect connecting the third active area, the fourth active area, and the first gate via a first EC contact located on the first gate.

摘要翻译： 本发明提供了一种改进的SRAM单元设计。 SRAM单元包括位于SRAM单元的第一垂直侧的第一导电阱中的氧化物上的第一有源区，位于SRAM单元的第一垂直侧的第二导电阱中的氧化物上的第二有源区， 位于SRAM单元的第二垂直侧的第一导电阱中的氧化物上的有源区，位于SRAM单元的第二垂直侧的第二导电阱中的氧化物上的第四有源区，位于第一垂直方向上的第一栅极 位于SRAM单元的第二垂直侧的第二栅极，经由位于第二栅极上的第二EC触点连接第一有源区域，第二有源区域和第二栅极的第一局部互连， 以及经由位于第一门上的第一EC触点连接第三有源区域，第四有源区域和第一栅极的第二局部互连。