公开(公告)号：US20060119607A1

公开(公告)日：2006-06-08

申请号：US11339937

申请日：2006-01-25

申请人： John Lindholm ,  John Nickolls ,  Simon Moy ,  Brett Coon

发明人： John Lindholm ,  John Nickolls ,  Simon Moy ,  Brett Coon

IPC分类号： G06T11/40 ,  G09G5/00

CPC分类号： G06T11/60 ,  G09G5/363

摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

摘要翻译： 图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。 专用纹理请求缓冲区排队相对较小的纹理命令和参数。 另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。 纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。 纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。 因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

公开(公告)号：US20050138328A1

公开(公告)日：2005-06-23

申请号：US10742514

申请日：2003-12-18

申请人： Simon Moy ,  John Lindholm

发明人： Simon Moy ,  John Lindholm

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3851

摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions are fetched into an instruction buffer that is configured to store an instruction from each of the threads. A dispatch circuit determines which instructions in the buffer are ready to execute and may issue any ready instruction for execution. An instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched into the buffer first. Once an instruction from a particular thread has issued, the fetch circuit fills the available buffer location with the following instruction from that thread.

摘要翻译： 诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。 指令被读取到指令缓冲区中，该缓冲器被配置为存储来自每个线程的指令。 调度电路确定缓冲器中的哪些指令准备好执行，并且可以发出任何可用的执行指令。 无论哪个指令首先被提取到缓冲区，可以在来自另一个线程的指令之前发出来自一个线程的指令。 一旦来自特定线程的指令已经发出，则获取电路使用该线程中的以下指令来填充可用的缓冲器位置。

公开(公告)号：US20140253567A1

公开(公告)日：2014-09-11

申请号：US13699658

申请日：2011-12-14

申请人： Simon Moy ,  Shihao Wang ,  Zhengqian Qiu

发明人： Simon Moy ,  Shihao Wang ,  Zhengqian Qiu

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G06F9/5011 ,  G06F2209/507 ,  Y02D10/22

摘要： The invention relates to a method for hiding texture latency in an MVP processor, which comprises the following steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with same length, and binding the register sets to the dies at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a PC (Program Counter) value in the case of return; and returning texture detail and allowing the shader thread to restart running. The invention also relates to a method for managing registers of grahic processing threads in the MVP processor.

摘要翻译： 本发明涉及一种在MVP处理器中隐藏纹理延迟的方法，包括以下步骤：允许MVP处理器开始运行主渲染程序; 根据长度设置，在MVP处理器中分割各种MVP内核实例的寄存器，获取具有相同长度的多个寄存器组，并且在内核实例的运行开始时将寄存器组绑定到管芯; 允许着色线程在发送纹理细节请求之后放弃着色器线程占用的处理时隙，并在返回时设置PC（程序计数器）值; 并返回纹理细节，并允许着色器线程重新启动。 本发明还涉及用于管理MVP处理器中的外加处理线程的寄存器的方法。

公开(公告)号：US20080082797A1

公开(公告)日：2008-04-03

申请号：US11538070

申请日：2006-10-03

申请人： Wing Yee LO ,  Simon Moy

发明人： Wing Yee LO ,  Simon Moy

IPC分类号： G06F15/00

CPC分类号： G06F15/8007 ,  G06F9/3004 ,  G06F9/383 ,  G06F9/3885 ,  G06F9/3887

摘要： Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of processing elements (PEs) and to perform instruction variances by the PEs. A CSIMD instruction is received, comprising a command and an index to the lookup table (LUT), to be executed by the PEs. The command of the received CSIMD instruction is executed in parallel differently by the PEs using the LUT index to randomly access the memory locations.

摘要翻译： 公开了用于处理可配置单指令多数据（CSIMD）指令的方法和装置。 在该方法中，提供存储信息的查找表（LUT）以支持与多个处理元件（PE）相关联的存储器位置的随机存取，并且由PE执行指令变化。 接收CSIMD指令，包括要由PE执行的查询表（LUT）的命令和索引。 通过使用LUT索引的PE不同地并行地执行所接收的CSIMD指令的命令来随机访问存储器位置。

公开(公告)号：US20070214343A1

公开(公告)日：2007-09-13

申请号：US11548272

申请日：2006-10-10

申请人： John Lindholm ,  Brett Coon ,  Simon Moy

发明人： John Lindholm ,  Brett Coon ,  Simon Moy

IPC分类号： G06F9/45

CPC分类号： G06F9/3802 ,  G06F9/3851

摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.

摘要翻译： 诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。 提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。 调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。 如果有多个功能单元可用，则可以并行调度多个指令。

公开(公告)号：US20050190195A1

公开(公告)日：2005-09-01

申请号：US10789735

申请日：2004-02-27

申请人： John Lindholm ,  John Nickolls ,  Simon Moy ,  Brett Coon

发明人： John Lindholm ,  John Nickolls ,  Simon Moy ,  Brett Coon

IPC分类号： G06T11/60 ,  G09G5/36 ,  G06T1/00 ,  G06T15/00 ,  G09G5/00

CPC分类号： G06T11/60 ,  G09G5/363

摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

摘要翻译： 图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。 专用纹理请求缓冲区排队相对较小的纹理命令和参数。 另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。 纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。 纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。 因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。