公开(公告)号：US5210437A

公开(公告)日：1993-05-11

申请号：US925411

申请日：1992-08-10

申请人： Shizuo Sawada ,  Seiko Iwasaki

发明人： Shizuo Sawada ,  Seiko Iwasaki

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10

CPC分类号： H01L29/66575 ,  H01L21/266 ,  H01L21/823456 ,  H01L29/1041 ,  H01L29/1045

摘要： The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.

摘要翻译： 本发明提供一种半导体器件，其具有通过使用其中与开口直径相对应的部分的掩模图案宽度等于或小于阱层的扩散深度的两倍的掩模形成在半导体衬底中的阱，以及 形成为具有作为MOS晶体管的沟道区的阱层的栅电极。 以这种方式形成的阱具有基本上半圆形的部分，以促进衬底表面中的杂质浓度控制。 当在单个掩模中形成具有小图案宽度的多种类型的开口图案时，可以在单个工艺中形成具有不同阈值电压的MOS晶体管。

公开(公告)号：US5144388A

公开(公告)日：1992-09-01

申请号：US664827

申请日：1991-03-05

申请人： Shizuo Sawada ,  Masaki Ogihara

发明人： Shizuo Sawada ,  Masaki Ogihara

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/7831

摘要： According to this invention, in an element region formed in a semiconductor substrate, a plurality of regions for constituting one electrode of source and drain electrodes of an FET are formed. A gate electrode is formed to surround the plurality of regions. The other electrode of the FET is formed in the element region except for the plurality of regions surrounded by the gate electrode.

公开(公告)号：US5111275A

公开(公告)日：1992-05-05

申请号：US286018

申请日：1988-12-19

申请人： Shizuo Sawada ,  Masaki Ogihara

发明人： Shizuo Sawada ,  Masaki Ogihara

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10805 ,  H01L23/528 ,  H01L2924/0002

摘要： A semiconductor device is disclosed which connects a bit line via a bit line contact to cells in a dynamic access memory which are constructed of a transistor and capacitor. The semiconductor device includes a first conductive layer connected to the cell of a cell array via a bit line contact and a second conductive layer connected to the first conductive layer via a contact hole which is formed over the first conductive layer. By providing the first conductive layer between the bit line contact and the bit line, it is possible to increase a flat line width around a bit line contact and hence to adequately lower the bit line's resistance.

摘要翻译： 公开了一种半导体器件，其将位线经由位线接触连接到由晶体管和电容器构成的动态存取存储器中的单元。 半导体器件包括通过位线接触连接到单元阵列的单元的第一导电层和经由形成在第一导电层上的接触孔连接到第一导电层的第二导电层。 通过在位线接触和位线之间提供第一导电层，可以增加位线接触周围的平坦线宽度，从而充分降低位线的电阻。