公开(公告)号：US20070291553A1

公开(公告)日：2007-12-20

申请号：US11755165

申请日：2007-05-30

申请人： Sung-Ryul Kim

发明人： Sung-Ryul Kim

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals thereof onto an output terminal responsive to selective invocation of the plurality of clock signals. The clock signals are invoked in an order based on the at least a portion of the memory column address.

摘要翻译： 用于集成电路存储器件的数据输出电路包括一个控制电路，该控制电路被配置为响应于存储器列地址的至少一部分产生多个时钟信号;以及多路复用器电路，被配置为输出在输入端上接收的存储器数据 其端子响应于选择性地调用多个时钟信号而输出到输出端上。 基于存储器列地址的至少一部分的顺序调用时钟信号。

公开(公告)号：US20060181946A1

公开(公告)日：2006-08-17

申请号：US11319247

申请日：2005-12-27

申请人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

发明人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/1204

摘要： A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.

摘要翻译： 具有开放位线架构的全压力可测试存储器件和测试存储器件的方法。 本发明的存储器件包括虚拟位线和连接到虚拟位线的电压控制器。 电压控制器在测试模式期间交替地向虚拟位线提供第一可变控制电压和第二可变控制电压。 根据测试存储器件的方法，在正常操作模式期间，将固定电压提供给边缘子阵列的虚拟位线。 然而，在测试模式期间，施加到虚拟位线的固定电压被替换为电源电压和/或接地电压，使得可以对所有子阵列进行同样的测试。

公开(公告)号：US07031201B2

公开(公告)日：2006-04-18

申请号：US11005544

申请日：2004-12-06

申请人： Sung-Ryul Kim ,  Dae-Hee Jung

发明人： Sung-Ryul Kim ,  Dae-Hee Jung

IPC分类号： G11C7/00

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/413 ,  G11C2207/107 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a memory cell array, a plurality of data input lines configured to convey data to the memory cell array and a plurality of data output lines configured to convey data from the memory cell array. The device also includes a memory write buffer that receives write data for the memory cell array and responsively drives the data input lines, a sense amplifier and a plurality of sense amplifier input lines configured to convey data to the sense amplifier. The device further includes a selecting circuit coupled to the data input lines, to the data output lines and to the sense amplifier input lines and configured to selectively couple the data input lines to the sense amplifier input lines responsive to a control signal.

摘要翻译： 集成电路存储器件包括存储单元阵列，被配置为将数据传送到存储单元阵列的多条数据输入线以及被配置为从存储单元阵列传送数据的多条数据输出线。 该装置还包括存储器写入缓冲器，其接收存储单元阵列的写入数据并且响应地驱动数据输入线，读出放大器和多个读出放大器输入线，其被配置为将数据传送到读出放大器。 该装置还包括耦合到数据输入线，数据输出线和读出放大器输入线的选择电路，并且被配置成响应于控制信号将数据输入线选择性地耦合到读出放大器输入线。