公开(公告)号：US07743355B2

公开(公告)日：2010-06-22

申请号：US11942034

申请日：2007-11-19

申请人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US07093208B2

公开(公告)日：2006-08-15

申请号：US10842589

申请日：2004-05-10

申请人： Patrick M. Williams ,  Ee K. Cho ,  David J. Hathaway ,  Mei-Ting Hsu ,  Lawrence K. Lange ,  Gregory A. Northrop ,  Chandramouli Visweswariah ,  Cindy ShuiKing Washburn ,  Jun Zhou

发明人： Patrick M. Williams ,  Ee K. Cho ,  David J. Hathaway ,  Mei-Ting Hsu ,  Lawrence K. Lange ,  Gregory A. Northrop ,  Chandramouli Visweswariah ,  Cindy ShuiKing Washburn ,  Jun Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.

摘要翻译： 可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。 该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。 为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。 调整受限于将设计映射回固定单元格时最小化“合并错误”。 此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。 在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。 特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。 最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

公开(公告)号：US07003747B2

公开(公告)日：2006-02-21

申请号：US10435824

申请日：2003-05-12

申请人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路的定时闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US06826733B2

公开(公告)日：2004-11-30

申请号：US10159921

申请日：2002-05-30

申请人： David J. Hathaway ,  Xiaoliang Bai ,  Chandramouli Visweswariah ,  Philip N. Strenski

发明人： David J. Hathaway ,  Xiaoliang Bai ,  Chandramouli Visweswariah ,  Philip N. Strenski

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design. The method for optimizing the design includes the steps of: defining an objective function computed from variables and functions of the design of the chip or system; deriving a merit function from the objective function by adding to it a plurality of separation terms; and minimizing the merit function which reduces the expected value of the objective function when confronted with significant variations of the design variables and functions.

摘要翻译： 描述了通过在存在设计参数的变化的情况下降低包含多个约束的成本函数来优化芯片或系统的设计的方法。 该方法利用数值优化，模拟退火或任何其他目标驱动的优化手段，并考虑了设计变量和功能建模中的不确定性。 即使在不能满足所有设计限制的情况下，也可以在优化过程结束时，大大减少设计限制的数量。 该优化还减少了设计操作的周期时间，并且在存在不能被设计的元件引入的延迟不可模拟或不可预测的变化的变化的情况下限制特定实现的最小操作周期时间的增加。 用于优化设计的方法包括以下步骤：定义从芯片或系统的设计的变量和功能计算的目标函数; 通过向目标函数中加入多个分离项，从而得出优点函数; 并且在面对设计变量和功能的显着变化时，最小化功能降低了目标函数的期望值。

公开(公告)号：US08607176B2

公开(公告)日：2013-12-10

申请号：US13088688

申请日：2011-04-18

申请人： Jeffrey P. Soreff ,  Bhavana Agrawal ,  David J. Hathaway

发明人： Jeffrey P. Soreff ,  Bhavana Agrawal ,  David J. Hathaway

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.

摘要翻译： 一种用于构建延迟规则的方法，其中包括MIS模拟对静态时序分析的影响，降低成本。 本方法包括构建歪斜窗口，用于纯粹来自SIS数据的MIS惩罚，并根据使用案例中的倾斜度接近偏斜窗口的边缘来缩小规则使用期间的MIS惩罚。 该方法既适用于电路库的定时规则构造，也适用于宏的定时规则构造，其中宏中仅部分电路可能对宏输入之间的偏移敏感。

公开(公告)号：US08239794B2

公开(公告)日：2012-08-07

申请号：US12568985

申请日：2009-09-29

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5022

摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

摘要翻译： 公开了用于估计电子电路的漏电流的系统和相关方法的实施例。 实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络） 并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。 然后，使用该信息，实施例估计电子电路的漏电流。 这是通过首先确定每个受驱动网络边界分区的每个状态的驱动网络边界分区的泄漏电流以及在电子电路运行期间该状态将在该被驱动的有界分区中发生的概率来实现的。 然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。 然后汇总结果。

公开(公告)号：US08015526B2

公开(公告)日：2011-09-06

申请号：US12138871

申请日：2008-06-13

申请人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

发明人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

公开(公告)号：US07890906B2

公开(公告)日：2011-02-15

申请号：US12117761

申请日：2008-05-09

申请人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

发明人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

公开(公告)号：US07469395B2

公开(公告)日：2008-12-23

申请号：US11952544

申请日：2007-12-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。 第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度 线。

公开(公告)号：US07401307B2

公开(公告)日：2008-07-15

申请号：US10904309

申请日：2004-11-03

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。