公开(公告)号：US08239794B2

公开(公告)日：2012-08-07

申请号：US12568985

申请日：2009-09-29

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5022

摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

摘要翻译： 公开了用于估计电子电路的漏电流的系统和相关方法的实施例。 实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络） 并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。 然后，使用该信息，实施例估计电子电路的漏电流。 这是通过首先确定每个受驱动网络边界分区的每个状态的驱动网络边界分区的泄漏电流以及在电子电路运行期间该状态将在该被驱动的有界分区中发生的概率来实现的。 然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。 然后汇总结果。

公开(公告)号：US20110077882A1

公开(公告)日：2011-03-31

申请号：US12568985

申请日：2009-09-29

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

IPC分类号： G06F19/00 ,  G01R27/00

CPC分类号： G06F17/5022

摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

摘要翻译： 公开了用于估计电子电路的漏电流的系统和相关方法的实施例。 实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络） 并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。 然后，使用该信息，实施例估计电子电路的漏电流。 这是通过首先确定每个受驱动网络边界分区的每个状态，驱动网络边界分区的泄漏电流以及在电子电路运行期间状态将在驱动网络划分区域内发生的概率来实现的。 然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。 然后汇总结果。

公开(公告)号：US08655634B2

公开(公告)日：2014-02-18

申请号：US12721227

申请日：2010-03-10

申请人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

发明人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/509 ,  G06F2217/84

摘要： A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

摘要翻译： 一种用于建模晶体管网络中负载CCC（通道连接部件）的负载影响的系统，方法和程序产品。 公开了一种系统，其包括分析系统，该分析系统确定负载CCC中针对正在确定负载条件的驱动CCC的转变或状态的网络的允许逻辑状态和转换功能; 跟踪系统，从一组输入端子遍历负载CCC中的路径; 以及元件替换系统，其替换负载CCC中的电路元件以创建建模的CCC，其中电路元件替换基于沿着跟踪遇到的电路元件的类型，以及连接到遇到的电路元件的网络的状态和转换功能 。

公开(公告)号：US20110224965A1

公开(公告)日：2011-09-15

申请号：US12721227

申请日：2010-03-10

申请人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

发明人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/509 ,  G06F2217/84

摘要： A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

摘要翻译： 一种用于建模晶体管网络中负载CCC（通道连接部件）的负载影响的系统，方法和程序产品。 公开了一种系统，其包括分析系统，该分析系统确定负载CCC中针对正在确定负载条件的驱动CCC的转变或状态的网络的允许逻辑状态和转换功能; 跟踪系统，从一组输入端子遍历负载CCC中的路径; 以及元件替换系统，其替换负载CCC中的电路元件以创建建模的CCC，其中电路元件替换基于沿着跟踪遇到的电路元件的类型，以及连接到遇到的电路元件的网络的状态和转换功能 。

公开(公告)号：US08037433B2

公开(公告)日：2011-10-11

申请号：US12196471

申请日：2008-08-22

申请人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

发明人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.

摘要翻译： 分析半导体电路的布局以计算可以包括迁移率偏移和阈值电压偏移的依赖于布局的参数。 影响依赖于布局的参数的依赖于布局的效应可能包括应力影响，快速热退火（RTA）效应和平版印刷效应。 计算不反映与布局有关的影响的内在函数，然后根据与布局相关的参数计算缩放修正符号。 通过将每个内在函数与相应的缩放参数相乘来获得反映与布局相关的效应的模型输出函数。

公开(公告)号：US08825455B2

公开(公告)日：2014-09-02

申请号：US13289589

申请日：2011-11-04

申请人： Calvin J. Bittner ,  Peter Feldmann ,  Richard D. Kimmel ,  Tong Li ,  Ali Sadigh ,  David W. Winston

发明人： Calvin J. Bittner ,  Peter Feldmann ,  Richard D. Kimmel ,  Tong Li ,  Ali Sadigh ,  David W. Winston

IPC分类号： G06F17/10 ,  G06F17/17

CPC分类号： G06F17/175

摘要： An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

摘要翻译： 提供了半导体器件评估的按需表模型。 一种提供用于半导体器件评估的按需表模型的方法，包括测量半导体器件的实例的一个或多个测量值。 所述方法还包括在接收到半导体器件评估的请求时由处理器提供用于半导体器件评估的实例的表模型。 所述方法还包括在所述表模型中生成所述一个或多个测量值的表条目，所述表条目包括所述实例的评估函数的一个或多个评估值。

公开(公告)号：US20100050138A1

公开(公告)日：2010-02-25

申请号：US12196471

申请日：2008-08-22

申请人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

发明人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.

摘要翻译： 分析半导体电路的布局以计算可以包括迁移率偏移和阈值电压偏移的依赖于布局的参数。 影响依赖于布局的参数的依赖于布局的效应可能包括应力影响，快速热退火（RTA）效应和平版印刷效应。 计算不反映与布局有关的影响的内在函数，然后根据与布局相关的参数计算缩放修正符号。 通过将每个内在函数与相应的缩放参数相乘来获得反映与布局相关的效应的模型输出函数。