Semiconductor package having an interposer in which one or more dies are formed and method of forming the same

    公开(公告)号:US12136597B2

    公开(公告)日:2024-11-05

    申请号:US17515864

    申请日:2021-11-01

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.

    CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

    公开(公告)号:US20220392839A1

    公开(公告)日:2022-12-08

    申请号:US17886704

    申请日:2022-08-12

    Applicant: MediaTek Inc.

    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

    FAN-OUT PACKAGE STRUCTURE WITH INTEGRATED ANTENNA

    公开(公告)号:US20210273317A1

    公开(公告)日:2021-09-02

    申请号:US17321914

    申请日:2021-05-17

    Applicant: MediaTek Inc.

    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

    Fan-out package structure with integrated antenna

    公开(公告)号:US11043730B2

    公开(公告)日:2021-06-22

    申请号:US16387354

    申请日:2019-04-17

    Applicant: MediaTek Inc.

    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.

    Semiconductor package with antenna and fabrication method thereof

    公开(公告)号:US11024954B2

    公开(公告)日:2021-06-01

    申请号:US16399659

    申请日:2019-04-30

    Applicant: MediaTek Inc.

    Abstract: A method of forming a semiconductor package structure includes providing a first wafer-level package structure having a die region surrounded by a scribe line region. The first wafer-level package structure includes a first encapsulating layer, a first redistribution layer (RDL) structure formed on the first encapsulating layer, a first antenna element formed in the first RDL structure and corresponding to the die region, and a semiconductor die in the first encapsulating layer and corresponding to the die region. A second wafer-level package structure is bonded onto the first RDL structure using a first adhesive layer. The second wafer-level package structure includes a second encapsulating layer attached to the first adhesive layer, and a second antenna element formed on the second encapsulating layer. The second antenna element and the first antenna element form a pitch antenna after the bonding of the second wafer-level package structure.

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