公开(公告)号：US20240170057A1

公开(公告)日：2024-05-23

申请号：US18425619

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

公开(公告)号：US11929138B2

公开(公告)日：2024-03-12

申请号：US17452717

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44

CPC classification number: G11C29/88 ,  G11C29/38 ,  G11C29/44

Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

公开(公告)号：US11923001B2

公开(公告)日：2024-03-05

申请号：US17580178

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/34 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

公开(公告)号：US11881284B2

公开(公告)日：2024-01-23

申请号：US17546431

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

CPC classification number: G11C7/1063

Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

公开(公告)号：US20230206997A1

公开(公告)日：2023-06-29

申请号：US17580178

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5671

Abstract: A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

公开(公告)号：US20230186959A1

公开(公告)日：2023-06-15

申请号：US17546431

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

CPC classification number: G11C7/1063

Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

公开(公告)号：US20220365883A1

公开(公告)日：2022-11-17

申请号：US17319497

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G06F12/1009

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, selecting, by the processing device, a first partition located on a first die of the memory device. The operations performed by the processing device further include selecting, based on a predefined partition offset reflecting a physical layout of the memory device, a second partition located on a second die of the memory device. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

公开(公告)号：US20220019501A1

公开(公告)日：2022-01-20

申请号：US16928710

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Jian Huang ,  Jiangli Zhu

IPC: G06F11/10 ,  G06F11/14 ,  G06F11/07 ,  G06F11/30 ,  G06F3/06

Abstract: An error associated with a read operation corresponding to a target memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. The first read throughput level is adjusted to a second read throughput level. A read retry operation associated with the target memory die is executed at the second read throughput level.