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    PADDING IN FLASH MEMORY BLOCKS
    31.
    发明申请
    PADDING IN FLASH MEMORY BLOCKS 有权

    公开(公告)号：US20240395329A1

    公开(公告)日：2024-11-28

    申请号：US18793392

    申请日：2024-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Murong Lang

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10

    Abstract: A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.

    Cross-temperature mitigation in a memory system
    32.
    发明授权
    Cross-temperature mitigation in a memory system 有权

    公开(公告)号：US12141467B2

    公开(公告)日：2024-11-12

    申请号：US17868085

    申请日：2022-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Murong Lang ,  Christina Papagianni ,  Zhenming Zhou ,  Ting Luo

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.

    SELECT GATE MAINTENANCE WITH ADAPTIVE SCAN FREQUENCY IN A MEMORY SUB-SYSTEM
    34.
    发明公开
    SELECT GATE MAINTENANCE WITH ADAPTIVE SCAN FREQUENCY IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240153570A1

    公开(公告)日：2024-05-09

    申请号：US18384716

    申请日：2023-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Murong Lang

    IPC: G11C16/34 ,  G11C16/26

    CPC classification number: G11C16/3495 ,  G11C16/26 ,  G11C16/3404

    Abstract: A processing device, operatively coupled with a memory device, determines a number of program/erase cycles performed on a block of the memory device. The processing device determines that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block. The processing device performs a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block. Responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, the processing device determines a rate of change associated with the current threshold voltage of the at least one select gate device. The processing device updates, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block.

    ADAPTIVE INTEGRITY SCAN IN A MEMORY SUB-SYSTEM
    36.
    发明公开
    ADAPTIVE INTEGRITY SCAN IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240062834A1

    公开(公告)日：2024-02-22

    申请号：US17891852

    申请日：2022-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0679 ,  G06F3/0629

    Abstract: A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event in the memory sub-system, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system. The processing device further determines a read margin associated with a first distribution of memory cells of the identified memory die, and determines an adaptive scan frequency for the identified memory die based on the read margin associated with the first distribution of memory cells.

    READ DISTURB MANAGEMENT
    39.
    发明公开
    READ DISTURB MANAGEMENT 审中-公开

    公开(公告)号：US20240029802A1

    公开(公告)日：2024-01-25

    申请号：US17871689

    申请日：2022-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Zhenming Zhou ,  Murong Lang ,  Li-Te Chang

    IPC: G11C16/34 ,  G11C11/406

    CPC classification number: G11C16/3418 ,  G11C16/349 ,  G11C11/40618

    Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

    Performing select gate integrity checks to identify and invalidate defective blocks
    40.
    发明授权
    Performing select gate integrity checks to identify and invalidate defective blocks 有权

    公开(公告)号：US11854644B2

    公开(公告)日：2023-12-26

    申请号：US17550462

    申请日：2021-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Murong Lang

    IPC: G11C16/34 ,  G11C29/50 ,  G06F3/06

    CPC classification number: G11C29/50004 ,  G06F3/0679

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.

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