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公开(公告)号:US11861370B2
公开(公告)日:2024-01-02
申请号:US17646254
申请日:2021-12-28
Applicant: Micron Technology, Inc.
Inventor: Roberto Izzi , Luca Porzio , Dionisio Minopoli
IPC: G06F9/00 , G06F9/4401 , G06F3/06
CPC classification number: G06F9/4406 , G06F3/0604 , G06F3/0659 , G06F3/0679
Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.
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公开(公告)号:US20230069752A1
公开(公告)日:2023-03-02
申请号:US17646254
申请日:2021-12-28
Applicant: Micron Technology, Inc.
Inventor: Roberto Izzi , Luca Porzio , Dionisio Minopoli
IPC: G06F9/4401 , G06F3/06
Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.
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公开(公告)号:US20220350532A1
公开(公告)日:2022-11-03
申请号:US17243321
申请日:2021-04-28
Applicant: Micron Technology, Inc.
Inventor: Luca Porzio , Nadav Grosz , Roberto Izzi , Jonathan S. Parry
Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.
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公开(公告)号:US20220342737A1
公开(公告)日:2022-10-27
申请号:US17668210
申请日:2022-02-09
Applicant: Micron Technology, Inc.
Inventor: Luca Porzio , Alessandro Orlando , Danilo Caraccio , Roberto Izzi
Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.
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公开(公告)号:US11379153B2
公开(公告)日:2022-07-05
申请号:US16937213
申请日:2020-07-23
Applicant: Micron Technology, Inc.
Inventor: Luca Porzio , Roberto Izzi , Nicola Colella , Danilo Caraccio , Alessandro Orlando
Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.
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公开(公告)号:US11340808B2
公开(公告)日:2022-05-24
申请号:US16890511
申请日:2020-06-02
Applicant: Micron Technology, Inc.
Inventor: Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F3/06
Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
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公开(公告)号:US11249830B1
公开(公告)日:2022-02-15
申请号:US16993690
申请日:2020-08-14
Applicant: Micron Technology, Inc.
Inventor: Luca Porzio , Alessandro Orlando , Danilo Caraccio , Roberto Izzi
Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.
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公开(公告)号:US10705747B2
公开(公告)日:2020-07-07
申请号:US15927339
申请日:2018-03-21
Applicant: Micron Technology, Inc.
Inventor: Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora , Roberto Izzi , Paolo Amato , Daniele Balluchi , Luca Porzio
IPC: G06F3/06
Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.
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公开(公告)号:US20250077123A1
公开(公告)日:2025-03-06
申请号:US18830282
申请日:2024-09-10
Applicant: Micron Technology, Inc.
Inventor: Roberto Izzi , Luca Porzio , Marco Onorato
IPC: G06F3/06
Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.
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公开(公告)号:US20240402926A1
公开(公告)日:2024-12-05
申请号:US18678346
申请日:2024-05-30
Applicant: Micron Technology, Inc.
Inventor: Luca Porzio , Roberto Izzi , Christian M. Gyllenskog , Giuseppe Cariello , Jonathan S. Parry , Reshmi Basu
Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.
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