-
公开(公告)号：US20210183426A1
公开(公告)日：2021-06-17
申请号：US17185488
申请日：2021-02-25
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara
IPC: G11C11/22 , H01L27/11502 , G11C11/56 , H01L27/11514
Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.
-
公开(公告)号：US11004492B2
公开(公告)日：2021-05-11
申请号：US16869510
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： Kiyotake Sakurai , Yasushi Matsubara
Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.
-
公开(公告)号：US10957374B2
公开(公告)日：2021-03-23
申请号：US16878882
申请日：2020-05-20
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara
IPC: G11C11/22 , H01L27/11502 , G11C11/56 , H01L27/11514
Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.
-
公开(公告)号：US10902935B2
公开(公告)日：2021-01-26
申请号：US16102489
申请日：2018-08-13
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara
Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.
-
公开(公告)号：US10804225B2
公开(公告)日：2020-10-13
申请号：US16532140
申请日：2019-08-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasushi Matsubara
IPC: H01L23/02 , H01L23/64 , H01L23/00 , H01L25/07 , H01L25/18 , H02M7/00 , G11C5/14 , G11C11/4074 , G11C11/4072 , G11C11/408
Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.
-
Patent Agency Ranking
公开(公告)号：US10685694B2
公开(公告)日：2020-06-16
申请号：US16387220
申请日：2019-04-17
Applicant: Micron Technology, Inc.
Inventor： Kiyotake Sakurai , Yasushi Matsubara
Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.
-
公开(公告)号：US20200051659A1
公开(公告)日：2020-02-13
申请号：US16102489
申请日：2018-08-13
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara
Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.
-
公开(公告)号：US20190355677A1
公开(公告)日：2019-11-21
申请号：US16532140
申请日：2019-08-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasushi Matsubara
Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.
-
公开(公告)号：US20190051343A1
公开(公告)日：2019-02-14
申请号：US16054785
申请日：2018-08-03
Applicant: Micron Technology, Inc.
Inventor： Kiyotake Sakurai , Yasushi Matsubara
Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.
-
公开(公告)号：US12298838B2
公开(公告)日：2025-05-13
申请号：US17960718
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Ki-Jun Nam , Yantao Ma , Yasushi Matsubara , Takamasa Suzuki
IPC: G06F1/00 , G06F1/3234 , G06F1/3296 , G11C11/22
Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.
-
-
-
-
-
-
-
-
-
Search Results
51
records
(took 0.026 seconds)
