公开(公告)号：US11495484B2

公开(公告)日：2022-11-08

申请号：US17566690

申请日：2021-12-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

公开(公告)号：US20220336328A1

公开(公告)日：2022-10-20

申请号：US17850819

申请日：2022-06-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L27/11551 ,  H01L27/108 ,  H01L29/732 ,  H01L27/11526 ,  H01L27/118 ,  H01L29/10 ,  H01L29/808 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/78 ,  H01L21/74 ,  H01L23/544 ,  H01L23/34 ,  H01L23/50

Abstract: A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

公开(公告)号：US11437368B2

公开(公告)日：2022-09-06

申请号：US17717094

申请日：2022-04-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/06 ,  H01L23/66 ,  H01L27/146 ,  H01L27/15

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20220216070A1

公开(公告)日：2022-07-07

申请号：US17705392

申请日：2022-03-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065

Abstract: A 3D semiconductor device a first level, where the first level includes a first layer which includes first transistors, where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer which includes second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one first ElectroStatic Discharge (ESD) circuit, and where the first level includes at least one second ESD circuit.

公开(公告)号：US20220157983A1

公开(公告)日：2022-05-19

申请号：US17586730

申请日：2022-01-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes a plurality of capacitors.

公开(公告)号：US20220122877A1

公开(公告)日：2022-04-21

申请号：US17566690

申请日：2021-12-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

公开(公告)号：US11309292B2

公开(公告)日：2022-04-19

申请号：US17536019

申请日：2021-11-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L21/74 ,  H01L25/00 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer over the first silicon layer; a second metal layer over the first metal layer; a first level including a plurality of transistors over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer over the first level; a fourth metal layer over the third metal layer, where the fourth metal layer is aligned to the first metal layer with less than 40 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm.

公开(公告)号：US11251149B2

公开(公告)日：2022-02-15

申请号：US17485504

申请日：2021-09-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L21/46 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/544 ,  H01L25/00

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US20210407991A1

公开(公告)日：2021-12-30

申请号：US17472667

申请日：2021-09-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L23/36 ,  H01L23/50 ,  H01L23/60 ,  H01L21/324 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the third layer includes crystalline silicon; and at least one temperature sensor.

公开(公告)号：US20210358794A1

公开(公告)日：2021-11-18

申请号：US17384793

申请日：2021-07-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a second level including a plurality of second transistors, where the second level overlays the first level, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the plurality of second transistors is at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.